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100 条记录 (耗时 0.062 秒)

    Power management for a system on a chip (SoC)
    51.
    发明授权
    Power management for a system on a chip (SoC) 有权
    芯片系统的电源管理（SoC）

    公开(公告)号：US08286014B2

    公开(公告)日：2012-10-09

    申请号：US12079185

    申请日：2008-03-25

    申请人： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    发明人： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    摘要： In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
    53.
    发明申请
    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
    将非外围组件互连（PCI）资源集成到个人计算机系统中

    公开(公告)号：US20120233366A1

    公开(公告)日：2012-09-13

    申请号：US13477631

    申请日：2012-05-22

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System
    55.
    发明申请
    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
    将非外围组件互连（PCI）资源集成到个人计算机系统中

    公开(公告)号：US20110271021A1

    公开(公告)日：2011-11-03

    申请号：US13180697

    申请日：2011-07-12

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Device, system and method for communication with heterogenous physical layers
    57.
    发明授权
    Device, system and method for communication with heterogenous physical layers 有权
    用于与异质物理层进行通信的设备，系统和方法

    公开(公告)号：US09396152B2

    公开(公告)日：2016-07-19

    申请号：US13844280

    申请日：2013-03-15

    申请人： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

    发明人： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4282 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

    摘要： A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

    摘要翻译： 用于处理数据分组以用于通过不同相应通信协议的PHY层进行通信的设备。 在一个实施例中，该设备包括第一协议栈和第二协议栈，它们各自用于PCIe TM通信协议。 第一协议栈和第二协议栈可分别与设备的第一物理（PHY）层和第二PHY层接口。 第一协议栈和第二协议栈可以交换分组以促进通过第一PHY层和第二PHY层的通信。 在另一个实施例中，第一PHY层用于根据PCIe TM通信协议进行通信，第二PHY层用于根据另一种较低功率通信协议进行通信。

    Reducing Latency OF Unified Memory Transactions
    58.
    发明申请
    Reducing Latency OF Unified Memory Transactions 有权
    减少统一内存交易的延迟

    公开(公告)号：US20150067433A1

    公开(公告)日：2015-03-05

    申请号：US14317308

    申请日：2014-06-27

    申请人： Mahesh Wagh ,  Prashanth Kalluraya

    发明人： Mahesh Wagh ,  Prashanth Kalluraya

    IPC分类号： G06F13/16 ,  H04L1/00 ,  H04L1/16 ,  G06F13/42

    CPC分类号： G06F13/1631 ,  G06F13/4234 ,  H04L1/1867

    摘要： In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，装置包括消耗逻辑，用于请求和处理包括关键数据部分和第二数据部分的数据，所述数据存储在耦合到插入在所述装置和所述存储器之间的处理器的存储器中。 此外，该装置包括耦合到消费逻辑的协议栈逻辑，以经由处理器向存储器发出读请求，以响应于读请求来请求数据并接收多个完成。 在一个实施例中，协议栈逻辑包括完成处理逻辑，用于在完成之后完成协议栈处理之前将第一个完成的数据发送到消费逻辑。 描述和要求保护其他实施例。

    METHOD, APPARATUS, AND SYSTEM FOR IMPROVING RESUME TIMES FOR ROOT PORTS AND ROOT PORT INTEGRATED ENDPOINTS
    59.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR IMPROVING RESUME TIMES FOR ROOT PORTS AND ROOT PORT INTEGRATED ENDPOINTS 审中-公开
    方法，装置和系统，用于改进根部和根端口综合终点的恢复时间

    公开(公告)号：US20140281622A1

    公开(公告)日：2014-09-18

    申请号：US13835275

    申请日：2013-03-15

    申请人： Mahesh Wagh ,  Robert E. Gough

    发明人： Mahesh Wagh ,  Robert E. Gough

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4418 ,  G06F13/42 ,  H04L49/15 ,  Y02D10/151 ,  Y02D50/20

    摘要： A device is determined to be in a low power state. A transition from the low power state to an active state is initiated, where a fixed minimum recovery time is defined for transitions from the low power state to the active state. A capability of the device is identified corresponding to transition of the device from the low power state to the active state, and the transition of the device from the low power state to the active state is completed based at least in part on the capability, such that the transition is to be completed prior to expiration of the fixed minimum recovery time.

    摘要翻译： 确定设备处于低功率状态。 开始从低功率状态到活动状态的转变，其中定义了从低功率状态到活动状态的转换的固定的最小恢复时间。 对应于设备从低功率状态到活动状态的转变来识别设备的能力，并且至少部分地基于能力完成设备从低功率状态到活动状态的转变，例如 该转换将在固定的最短恢复时间到期之前完成。

    Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol
    60.
    发明申请
    Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol 有权

    公开(公告)号：US20140006670A1

    公开(公告)日：2014-01-02

    申请号：US13534541

    申请日：2012-06-27

    申请人： Mahesh Wagh

    发明人： Mahesh Wagh

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4027 ,  G06F13/385 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

    摘要： In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.