公开(公告)号：US07154146B2

公开(公告)日：2006-12-26

申请号：US11283015

申请日：2005-11-18

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

公开(公告)号：US20060199340A1

公开(公告)日：2006-09-07

申请号：US11406863

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt Beigel ,  Fred Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt Beigel ,  Fred Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US20060076619A1

公开(公告)日：2006-04-13

申请号：US11283015

申请日：2005-11-18

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices including a MOSFET having a dielectric plug. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

摘要翻译： 本发明提供了一种制造MOSFET中的电介质塞的技术。 本发明包括包括一个或多个器件的器件和系统，该器件和系统包括具有电介质插塞的MOSFET。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底，并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及源极之间的沟道区域 和漏区。

公开(公告)号：US20050269669A1

公开(公告)日：2005-12-08

申请号：US11185468

申请日：2005-07-19

申请人： Brent McClure ,  Casey Kurth ,  Shenlin Chen ,  Debra Gould ,  Lyle Breiner ,  Er-Xuan Ping ,  Fred Fishburn ,  Hongmei Wang

发明人： Brent McClure ,  Casey Kurth ,  Shenlin Chen ,  Debra Gould ,  Lyle Breiner ,  Er-Xuan Ping ,  Fred Fishburn ,  Hongmei Wang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L28/84 ,  H01L27/0805 ,  H01L27/10867 ,  H01L27/10873 ,  H01L28/75 ,  H01L28/91

摘要： A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

摘要翻译： 电容器结构包括第一电极和第一电极与支撑电容器结构的表面之间的层。 与其他相同的电容器结构相比，电容器结构可以表现出较低的RC时间常数。 或者或另外，第一电极可以包含Si，并且该层可以限制Si对第一电极和支撑表面之间的金属硅化物材料的形成有贡献。 该层可以是氮化物层，并且可以是导电的或绝缘的。 当导电时，该层可以表现出大于第一电极的第二电导率的第一电导率。 电容器结构可用于存储器件中。

公开(公告)号：US20050123920A1

公开(公告)日：2005-06-09

申请号：US10506266

申请日：2003-03-06

申请人： Herbert Cohen ,  Mina Zhou ,  Hongmei Wang

发明人： Herbert Cohen ,  Mina Zhou ,  Hongmei Wang

IPC分类号： A61K38/00 ,  C07K14/47 ,  C12Q1/68 ,  C07H21/04 ,  G01N33/574

CPC分类号： C07K14/4747 ,  A61K38/00

摘要： The present invention provides isolated and substantially purified nucleic acids encoding human Jade-1 (for “gene” for Apoptosis and Differentiation in Epithelia) and related nucleic acids. The invention further provides Jade protein, which, when expressed in a eukaryotic cell, has an apparent molecular weight of 64 kD. We have discovered that Jade protein functions 1 apoptosis and regulation of cell cycle as well as in cellular differentiation process. Accordingly, the Jade-family of genes and their gene products provide novel diagnostic and prognostic tools for identifying and/or classifying diseases involving abnormal apoptosis and defective cell cycle.

摘要翻译： 本发明提供了分离和基本上纯化的编码人类玉-1的核酸（用于上皮细胞凋亡和分化的“基因”）和相关核酸。 本发明还提供了玉质蛋白，当在真核细胞中表达时，其表观分子量为64kD。 我们发现玉石蛋白质能够起到细胞凋亡和调节细胞周期以及细胞分化过程的作用。 因此，翡翠家族的基因及其基因产物为识别和/或分类涉及异常细胞凋亡和缺陷细胞周期的疾病提供了新的诊断和预后工具。