公开(公告)号：US07385834B2

公开(公告)日：2008-06-10

申请号：US11444355

申请日：2006-06-01

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/1052

摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n

摘要翻译： 在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。 。 。 n，n + 1，。 。 。 ，m-1，m}，其中M，n和m是正整数，并且其中n

公开(公告)号：US20080013377A1

公开(公告)日：2008-01-17

申请号：US11729169

申请日：2007-03-28

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3427

摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.

摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。 第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。 第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。 此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。 此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。 还讨论了相关方法。

公开(公告)号：US20070257302A1

公开(公告)日：2007-11-08

申请号：US11797401

申请日：2007-05-03

申请人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

发明人： Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Ju-Hyung Kim ,  Sang-Hun Jeon

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

摘要翻译： 半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞 使多晶硅层通过开口接触。

公开(公告)号：US20070075336A1

公开(公告)日：2007-04-05

申请号：US11376371

申请日：2006-03-15

申请人： Jong-Sun Sel ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi

IPC分类号： H01L27/10

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S257/905

摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.

摘要翻译： 闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。 亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。 位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。 在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

公开(公告)号：US20060208338A1

公开(公告)日：2006-09-21

申请号：US11375983

申请日：2006-03-15

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20060208302A1

公开(公告)日：2006-09-21

申请号：US11354535

申请日：2006-02-15

申请人： Yoo-Cheol Shin ,  Jung-Dal Choi ,  Ki-Tae Park ,  Jong-Sun Sel

发明人： Yoo-Cheol Shin ,  Jung-Dal Choi ,  Ki-Tae Park ,  Jong-Sun Sel

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate field region to define the active region and has a protrusion higher than a top surface of the semiconductor substrate active region. A memory storage pattern is formed which crosses and extends from the semiconductor substrate active region to cover sidewalls of the protrusion of the trench isolation layer. A gate electrode is formed on the memory storage pattern and extends upward from the trench isolation layer.

摘要翻译： 提供了具有电荷陷阱层的非易失性存储器件及其制造方法。 非易失性存储器件包括具有有源区和与有源区接触的场区的半导体衬底。 沟槽隔离层形成在半导体衬底场区内，以限定有源区，并具有高于半导体衬底有源区的顶表面的突起。 形成存储器存储图案，其跨越并从半导体衬底有源区域延伸以覆盖沟槽隔离层的突起的侧壁。 栅电极形成在存储器存储图案上并从沟槽隔离层向上延伸。

公开(公告)号：US07084440B2

公开(公告)日：2006-08-01

申请号：US10376465

申请日：2003-02-28

申请人： Jong-Sun Sel ,  Hong-Soo Kim ,  Jung-Dal Choi

发明人： Jong-Sun Sel ,  Hong-Soo Kim ,  Jung-Dal Choi

IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L23/58 ,  H01L29/76

CPC分类号： H01L27/0207 ,  H01L27/115

摘要： An integrated circuit layout and a semiconductor device manufactured using the same are provided. According to one embodiment, a semiconductor device has a substrate and a plurality of bar type patterns on the substrate. The bar type patterns are substantially parallel to each other. At least one of the bar type patterns includes first and second ends and a middle part therebetween. The bar type patterns has an overhang at the first end thereof. The bar type patterns may be gate patterns, bit line patterns or active patterns.

公开(公告)号：US06806518B2

公开(公告)日：2004-10-19

申请号：US10794508

申请日：2004-03-05

申请人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

发明人： Hong-Soo Kim ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yong-Joon Choi

IPC分类号： H01L2710

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.

公开(公告)号：US07666717B2

公开(公告)日：2010-02-23

申请号：US11538839

申请日：2006-10-05

申请人： Jong-Sun Sel ,  Sung-Nam Chang ,  Dae-Woong Kang ,  Bong-Tae Park

发明人： Jong-Sun Sel ,  Sung-Nam Chang ,  Dae-Woong Kang ,  Bong-Tae Park

IPC分类号： H01L21/82

CPC分类号： H01L27/11521 ,  H01L23/5258 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.

摘要翻译： 非易失性器件包括具有熔丝窗口区域的半导体衬底。 至少有一个保险丝穿过保险丝窗口区域。 场区域布置在保险丝窗口区域的外部并且布置在至少一个保险丝的端部下方。 隔离层被配置为隔离场区域。 保险丝绝缘层介于至少一个保险丝和场区之间。

公开(公告)号：US07572684B2

公开(公告)日：2009-08-11

申请号：US11646217

申请日：2006-12-27

申请人： Jung-Dal Chol ,  Jong-Sun Sel ,  Chang-Seok Kang

发明人： Jung-Dal Chol ,  Jong-Sun Sel ,  Chang-Seok Kang

IPC分类号： H01L21/335

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  Y10S257/903

摘要： Nonvolatile memory devices, and methods of forming the same are disclosed. A memory device includes a substrate having a cell region, a low voltage region and a high voltage region. A ground selection transistor, a string selection transistor and a cell transistor are in the cell region, a low voltage transistor is in the low voltage region, and a high voltage transistor is in the high voltage region. A common source contact is on the ground selection transistor and a low voltage contact is on the low voltage transistor. A bit line contact is on the string selection transistor, a high voltage contact is on the high voltage transistor, and a bit line is on the bit line contact. A first insulating layer is on the substrate, and a second insulating layer is on the first insulating layer. The common source contact and the first low voltage contact extend to a height of the first insulating layer, and the bit line contact and the first high voltage contact extend to a height of the second insulating layer.

摘要翻译： 公开了非易失性存储器件及其形成方法。 存储器件包括具有单元区域，低电压区域和高电压区域的衬底。 接地选择晶体管，串选择晶体管和单元晶体管在单元区域中，低电压晶体管处于低电压区域，高压晶体管处于高电压区域。 公共源触点位于接地选择晶体管上，低压触点位于低压晶体管上。 串行选择晶体管上有一个位线接点，高电压晶体管上有高压触点，位线接触位线。 第一绝缘层在基板上，第二绝缘层位于第一绝缘层上。 共源极接触和第一低电压接触延伸到第一绝缘层的高度，并且位线接触和第一高电压接触延伸到第二绝缘层的高度。