公开(公告)号：US20060143259A1

公开(公告)日：2006-06-29

申请号：US11359201

申请日：2006-02-22

Applicant: Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC: G06F7/38

CPC classification number: G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

公开(公告)号：US20060039492A1

公开(公告)日：2006-02-23

申请号：US11256182

申请日：2005-10-21

Applicant: Kameran Azadet ,  Erich Haratsch

Inventor： Kameran Azadet ,  Erich Haratsch

IPC: H04L23/02

CPC classification number: H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.

公开(公告)号：US20050018777A1

公开(公告)日：2005-01-27

申请号：US10610335

申请日：2003-06-30

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H04L25/02 ,  H04B3/30 ,  H04B3/32 ,  H04L25/03 ,  H04B3/00

CPC classification number: H04B3/32 ,  H04B3/30

Abstract: A method and apparatus are disclosed for reducing noise, such as external noise, cross-talk and echo, in an unbalanced channel. A cross-talk canceller is disclosed that uses a multi-dimensional finite impulse response filter to process both the differential, d, and common-mode, c, components of a received signal. Recovery of the differential mode component of the received signal is improved by reducing the contribution of the common mode component. The common mode component of a received signal may be expressed, for example, as the average of two voltages or two current signals. The differential and common mode components of the received signal are equalized. The disclosed multi-dimensional cross-talk canceller reduces external noise; near-end crosstalk resulting from differential and common mode components on one twisted pair interfering with another twisted pair; and echo crosstalk resulting from differential and common mode cross-talk components on the same twisted pair.

Abstract translation: 公开了一种用于在不平衡通道中降低诸如外部噪声，串扰和回波之类的噪声的方法和装置。 公开了一种使用多维有限脉冲响应滤波器来处理接收信号的差分，差分和共模c分量的串扰消除器。 通过减小共模分量的贡献来提高接收信号的差模分量的恢复。 接收信号的共模分量可以例如表示为两个电压或两个电流信号的平均值。 接收信号的差分和共模分量相等。 所公开的多维串扰消除器减少外部噪声; 一对双绞线上的差模和共模分量产生的近端串扰干扰另一双绞线; 以及由相同双绞线上的差分和共模串扰组件产生的回声串扰。

公开(公告)号：US06617993B1

公开(公告)日：2003-09-09

申请号：US09414129

申请日：1999-10-08

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H03M156

CPC classification number: H03M1/56

Abstract: An A/D converter in which a thermometer code representing an increase in analog input voltage values is asynchronously derived using a chain of buffers, the thermometer code being translated using a binary code into a ramp voltage by a D/A converter and frozen when the ramp voltage equals the amplitude of a selected analog voltage being digitized.

Abstract translation: 一种A / D转换器，其中使用缓冲器链异步导出表示模拟输入电压值增加的温度计代码，使用二进制码将温度计代码转换为D / A转换器的斜坡电压并在 斜坡电压等于所选模拟电压的数字化幅度。

公开(公告)号：US06192072B1

公开(公告)日：2001-02-20

申请号：US09326781

申请日：1999-06-04

Applicant: Kameran Azadet ,  Meng-Lin Yu

Inventor： Kameran Azadet ,  Meng-Lin Yu

IPC: H03H730

CPC classification number: H04L25/03057 ,  H04L2025/0349

Abstract: A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel DFE groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.

Abstract translation: 公开了一种用于通过在选择（复用）阶段中组合块处理和先行技术来增加并行判决反馈均衡器（DFE）的有效处理速度的方法和装置。 本发明通过在选择阶段中使用先行技术来扩展并行DFE，以预先计算先前块对每个后续块的影响，从而消除串行输出依赖性。 并行DFE包括多路复用器树结构，其为每个块选择适当的输出值，并且预先计算先前块在每个后续块上的影响。 采用logN顺序的复用延迟算法来解决输出依赖关系，从而加快并行块处理DFE。 所公开的DFE架构可以与流水线结合，以完全消除关键路径问题。 流水线将所需的关键路径时序减少到一个复用时间。 所公开的用于并行DFE组多路复用器的多路复用器树电路块分成两组，被称为块对，并且为每个块提供至少一个多路复用器，i从可能的预计算值中选择输出值yi。 每个并行块的输出取决于由块的先行处理器生成的可能的预计算值，以及最终为每个先前块选择的实际值。 为了减少获得每个实际输出值的延迟，本发明假设每个块包含每个可能的值，并将假设传递给所有后续块。 因此，从可能值中选择的多路复用器的数量根据N.logN而增长，其中N是块号。

公开(公告)号：US09942078B2

公开(公告)日：2018-04-10

申请号：US12474344

申请日：2009-05-29

Applicant: Kameran Azadet ,  Samer Hijazi ,  Albert Molina ,  Ramon Sanchez

Inventor： Kameran Azadet ,  Samer Hijazi ,  Albert Molina ,  Ramon Sanchez

IPC: H04L27/26 ,  H04L25/02

CPC classification number: H04L27/2657 ,  H04L25/0202 ,  H04L27/2675 ,  H04L27/2695

Abstract: Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero.

公开(公告)号：US08856401B2

公开(公告)日：2014-10-07

申请号：US10880331

申请日：2004-06-29

Applicant: Kameran Azadet ,  Thomas Truman

Inventor： Kameran Azadet ,  Thomas Truman

IPC: H04J3/16 ,  G06F15/16 ,  G06F13/40 ,  H04L29/06

CPC classification number: G06F13/4022 ,  H04L69/14

Abstract: An integrated controller is provided for controlling communications with a plurality of peripheral devices. The integrated controller includes a bus interface for processing communications with a processor; a switch for routing communications between the processor and one or more of the peripheral devices; and a plurality of controllers, where each of the controllers provide an interface to at least one peripheral device. The controllers include at least one PHY controller for a corresponding peripheral device that provides an electrical interface to a connection, such as a network connection. The controllers also include at least one MAC controller that stores and forwards packets to and from a network connection.

Abstract translation: 提供集成控制器用于控制与多个外围设备的通信。 集成控制器包括用于处理与处理器的通信的总线接口; 用于路由处理器与一个或多个外围设备之间的通信的交换机; 以及多个控制器，其中每个控制器提供与至少一个外围设备的接口。 控制器包括至少一个PHY控制器，用于相应的外围设备，其提供诸如网络连接的连接的电接口。 控制器还包括至少一个MAC控制器，其存储和转发分组到网络连接和从网络连接转发分组。

公开(公告)号：US08699557B2

公开(公告)日：2014-04-15

申请号：US13082881

申请日：2011-04-08

Applicant: Erich F. Haratsch ,  Kameran Azadet

Inventor： Erich F. Haratsch ,  Kameran Azadet

IPC: H04L27/06

CPC classification number: H04L25/03235 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/4917

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract translation: 公开了一种流水线判决反馈单元（DFU），用于具有本地反馈的简化状态维特比检测器。 所公开的流水线判决反馈单元通过基于部分符号间干扰的估计的流水线计算提高了通过简化状态维特比检测器可以实现的最大数据速率。 因此公开了流水线判决反馈单元，其计算多个基于部分符号间干扰的估计，其中至少一个部分符号间干扰估计基于所选择的部分符号间干扰估计; 并且将所选择的部分符号间干扰估计从用于路径扩展的部分符号间干扰估计中选择为状态。

公开(公告)号：US08385489B2

公开(公告)日：2013-02-26

申请号：US12547298

申请日：2009-08-25

Applicant: Kameran Azadet ,  Samer Hijazi ,  Albert Molina ,  Joe H. Othmer ,  Ramon Sanchez

Inventor： Kameran Azadet ,  Samer Hijazi ,  Albert Molina ,  Joe H. Othmer ,  Ramon Sanchez

IPC: H04B1/10

CPC classification number: H04L25/0232 ,  H04L2025/03414

Abstract: Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain.

Abstract translation: 提供了在本征域中使用内插消除的无线信道估计的方法和装置。 已知OFDM符号位置处的信道分量被内插到其他OFDM符号位置。 提供了用于在参考信号（即，训练信号）之间的本征域内插入以降低复杂度来估计均衡器系数的方法和装置。 特别地，本发明的一个方面在本征域中的所需矩阵求逆之前执行所需的插值。

公开(公告)号：US08290462B2

公开(公告)日：2012-10-16

申请号：US12365444

申请日：2009-02-04

Applicant: Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

Inventor： Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

IPC: H04B1/06

CPC classification number: H04L25/0202 ,  H04L1/0631 ,  H04L1/20 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/021 ,  H04L25/022 ,  H04L25/023 ,  H04L25/025

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract translation: 在一个实施例中，提供接收机用于多输入系统，该多输入系统包括接收天线，其接收与从多个发射天线发射的多个信号相对应的时域信号。 接收机包括：（a）适于将时域信号变换为频域信号的变换单元; （b）信道估计单元，适于基于频域信号和频域导频信号估计与多个发射天线和接收天线之间的各个信道的多个传递函数相对应的组合传递函数 ; 以及（c）信道分离单元，其包括将所述组合传递函数分离成多个估计信道传递函数的多个频域卷积单元。