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公开(公告)号：US06236695B1
公开(公告)日：2001-05-22
申请号：US09316352
申请日：1999-05-21
申请人： Gregory F. Taylor
发明人： Gregory F. Taylor
IPC分类号： H04L2536
CPC分类号： H04L25/028 , H03K5/135 , H03K2005/00104 , H03K2005/0011
摘要： An output buffer circuit includes an adjustable delay time and is coupled to a reference output buffer which includes an adjustable delay time and a fixed delay time. In one embodiment, a synchronous delay line circuit provides a reference signal having a predetermined delay time. The time delay is equal to 1/N of a clock signal cycle. The reference output buffer uses the reference signal to set a cumulative delay time for the reference output buffer equal to 1/N. The adjustable delay time of the output buffer is set equal to the adjustable time delay of the reference output buffer.
摘要翻译： 输出缓冲器电路包括可调延迟时间，并且耦合到参考输出缓冲器，其包括可调节的延迟时间和固定的延迟时间。 在一个实施例中，同步延迟线电路提供具有预定延迟时间的参考信号。 时间延迟等于时钟信号周期的1 / N。 参考输出缓冲器使用参考信号设置参考输出缓冲区的累加延迟时间等于1 / N。 输出缓冲器的可调延迟时间设置为等于参考输出缓冲器的可调延时。
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公开(公告)号：US6124755A
公开(公告)日：2000-09-26
申请号：US941779
申请日：1997-09-29
CPC分类号： H03L7/0896
摘要： A method and an apparatus for biasing a charge pump in a phase locked loop in a circuit and generally for biasing a circuit through the use of a replica circuit. The method and apparatus make use of a replica circuit including substantially similar circuit elements to those circuit elements making up the circuit to be biased. Through the use of comparison and bias techniques, the replica circuit and the circuit to be biased are both biased. The bias conditions result from a comparison of the operation of the replica circuit and the circuit to be biased. Since the replica circuit operates in a manner substantially similar to an expected operation mode of the circuit to be biased, the bias conditions resulting from the comparisons will cause the circuit to be biased to operate similarly to how the replica circuit operates, while still handling external influences such as loading. Currents of two current sources within the circuit to be biased are equalized by biasing of one of the current sources responsive to the operation of both the circuit to be biased and a replica circuit. This equalization reduces the amount of error current erroneously added to or subtracted from a loop filter as a result of unequal currents flowing through the two current sources.
摘要翻译： 一种用于偏置电路中的锁相环中的电荷泵的方法和装置，并且通常通过使用复制电路来偏置电路。 该方法和装置利用复制电路，该复制电路包括与组成电路偏置的那些电路元件基本相似的电路元件。 通过使用比较和偏置技术，复制电路和要偏置的电路都是偏置的。 偏置条件是由复制电路的操作和要偏置的电路进行比较而产生的。 由于复制电路的操作方式与要偏置的电路的预期工作模式大致相同，所以比较所产生的偏置条件将导致电路被偏置以类似于复制电路的工作方式进行工作，同时仍然处理外部 影响如装载。 要偏置的电路中的两个电流源的电流通过响应于要偏置的电路和复制电路的操作的一个电流源的偏置来均衡。 该均衡减少了由于流过两个电流源的不相等的电流而错误地添加到环路滤波器或从环路滤波器中减去的误差电流的量。
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公开(公告)号：US06085345A
公开(公告)日：2000-07-04
申请号：US998487
申请日：1997-12-24
申请人： Gregory F. Taylor
发明人： Gregory F. Taylor
CPC分类号： G01R31/3016 , H03K5/26 , H03L7/0812
摘要： Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T.sub.setup and T.sub.hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.
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公开(公告)号：US5153848A
公开(公告)日：1992-10-06
申请号：US597364
申请日：1990-10-12
CPC分类号： G06F7/5318 , G06F7/483 , G06F7/4876 , G06F7/5338 , G06F7/544 , G06F2207/3884 , G06F2207/3896 , G06F2207/5442
摘要： In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.
摘要翻译： 在高速二进制乘法器电路中，被乘数被分割成一系列8位片，乘法器被修改 - 展位记录成3位组。 相应的部分乘积项在小进位存储加法器（CSA）单元的规则阵列中被减少。 CSA阵列的迭代使用提供了百分之七十的芯片面积或常规实现的加法器数量。 乘法器和分频器在内部流水线驱动，由用户透明的快速，两相内部时钟驱动。 内部时钟停止并在加载新的操作数和指令数据时重新启动，以将内部时钟同步到系统时钟。 本发明的其它方面包括用于操作和测试的两速内部时钟，系统时钟信号的双节点时钟停止和分布式缓冲。
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55.发明授权Methods and apparatus for determining the absolute value of the difference between binary operands 失效用于确定二进制操作数之间的差的绝对值的方法和装置
公开(公告)号：US4982352A
公开(公告)日：1991-01-01
申请号：US441040
申请日：1989-11-22
CPC分类号： G06F7/5318 , G06F7/483 , G06F7/4876 , G06F7/5338 , G06F7/544 , G06F2207/3884 , G06F2207/3896 , G06F2207/5442
摘要： In a floating point ALU, a carry-lookahead adder circuit includes integral XOR logic means for complementing the sum bits responsive to an invert signal for generating the absolute value of the difference between two binary operands without added gate delay.
摘要翻译： 在浮点ALU中，进位 - 前瞻加法器电路包括用于对反相信号进行补码的积分XOR逻辑装置，用于产生没有加上门延迟的两个二进制操作数之间的差的绝对值。
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