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公开(公告)号：US5832003A
公开(公告)日：1998-11-03
申请号：US638057
申请日：1996-04-25
申请人： Bob Elkind
发明人： Bob Elkind
CPC分类号： H04N17/02 , H04L1/20 , H04N17/004
摘要： A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.
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公开(公告)号：US5282034A
公开(公告)日：1994-01-25
申请号：US43092
申请日：1993-04-05
申请人： Bob Elkind , Kenneth M. Ainsworth , Gilbert A. Hoffman , Howard A. Landsman , Gary Sargeant , James L. Tallman
发明人： Bob Elkind , Kenneth M. Ainsworth , Gilbert A. Hoffman , Howard A. Landsman , Gary Sargeant , James L. Tallman
CPC分类号： H04N17/00
摘要： A bright video line select display for a waveform monitor is achieved by storing a selected line from a video frame of a digital video input signal. The stored selected line is iteratively substituted for a plurality of video lines during the vertical interval of the digital video input signal. When line select mode is selected, those video lines during the vertical interval are displayed as a waveform, resulting in a brighter display of the selected video line.
摘要翻译： 通过存储来自数字视频输入信号的视频帧的所选行来实现波形监视器的明亮视频行选择显示。 存储的所选行在数字视频输入信号的垂直间隔期间迭代地代替多个视频行。 当选择行选择模式时，垂直间隔期间的这些视频行显示为波形，导致所选视频行的显示更亮。
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公开(公告)号：US5153848A
公开(公告)日：1992-10-06
申请号：US597364
申请日：1990-10-12
CPC分类号： G06F7/5318 , G06F7/483 , G06F7/4876 , G06F7/5338 , G06F7/544 , G06F2207/3884 , G06F2207/3896 , G06F2207/5442
摘要： In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.
摘要翻译： 在高速二进制乘法器电路中，被乘数被分割成一系列8位片，乘法器被修改 - 展位记录成3位组。 相应的部分乘积项在小进位存储加法器（CSA）单元的规则阵列中被减少。 CSA阵列的迭代使用提供了百分之七十的芯片面积或常规实现的加法器数量。 乘法器和分频器在内部流水线驱动，由用户透明的快速，两相内部时钟驱动。 内部时钟停止并在加载新的操作数和指令数据时重新启动，以将内部时钟同步到系统时钟。 本发明的其它方面包括用于操作和测试的两速内部时钟，系统时钟信号的双节点时钟停止和分布式缓冲。
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公开(公告)号：US6119258A
公开(公告)日：2000-09-12
申请号：US47979
申请日：1998-03-25
申请人： Bob Elkind
发明人： Bob Elkind
CPC分类号： H04N17/02 , H04L1/20 , H04N17/004
摘要： A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.
摘要翻译： 视频误差/失真检查器从输入的重复数字信号和对应于输入的重复数字信号的参考数据信号产生差分信号。 将差分信号与最大和最小阈值进行比较，以在差信号超过任一阈值时产生误差信号。 该差分信号还用于产生与总范围值进行比较的运行范围值，以在重复数字信号的一次迭代期间产生误差信号，差分信号超过由总范围值定义的指定范围。 误差信号以视觉上或字母数字或两者适当地显示，使得操作者可以识别重复数字信号中的错误的类型，严重性和位置。
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公开(公告)号：US5949495A
公开(公告)日：1999-09-07
申请号：US639293
申请日：1996-04-25
摘要： Generation of digital cursors for serial digital television waveform monitors includes inputting hexadecimal values for the cursors by an operator via a front panel. The hexadecimal values are received by a microprocessor which loads them into appropriate registers of a co-processor. The outputs of the cursor registers in the co-processor are input to respective inputs of a multiplexer together with a digital signal representing a serial digital television signal. A select signal for the multiplexer is generated by a selection circuit that is enabled by a digital cursor ON command when the waveform monitor is in a cursor mode. The selection circuit at predetermined locations of the digital signal generates the select signal so that the appropriate cursor values are inserted into the digital signal at those locations. The processed digital signal from the co-processor is then converted to analog, filtered, and displayed on a display device to present a waveform representing the serial digital television signal together with the digital cursors.
摘要翻译： 串行数字电视波形监视器的数字光标的生成包括操作员通过前面板输入光标的十六进制值。 十六进制值由微处理器接收，微处理器将它们加载到协处理器的适当寄存器中。 协处理器中的光标寄存器的输出与表示串行数字电视信号的数字信号一起输入到多路复用器的相应输入端。 当波形监视器处于光标模式时，通过数字光标ON命令启用的选择电路产生多路复用器的选择信号。 在数字信号的预定位置处的选择电路产生选择信号，使得在那些位置处将适当的光标值插入到数字信号中。 然后将来自协处理器的经处理的数字信号转换为模拟，滤波和显示在显示设备上，以呈现与数字光标一起表示串行数字电视信号的波形。
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公开(公告)号：US5208666A
公开(公告)日：1993-05-04
申请号：US782927
申请日：1991-10-25
申请人： Bob Elkind , David Fibush , Kenneth M. Ainsworth
发明人： Bob Elkind , David Fibush , Kenneth M. Ainsworth
CPC分类号： H04N19/89 , H04N17/004
摘要： Error detection for digital television equipment that strips away the vertical and horizontal intervals of a digital video signal so that only the active picture portion of the digital video signal is determined by a digital test signal generated from the digital video signal. The digital test signal has replaced at a predetermined location in the active picture portion of the digital video signal one or more video data words with data values that represent check word data for the active picture portion. The check word data may be inserted into the beginning of one of the horizontal lines of the active picture portion of the next field, or may be modified and inserted into the end of the last line of the active picture portion of the same field of the digital video signal. A receiving instrument processes the output of the digital television instrument under test to generate active picture check word data. The active picture check word data is compared either with the check word data extracted from the predetermined location in the active picture portion of the digital test signal or with a predetermined value to determine whether there were any digital errors in processing of the digital test signal by the digital television equipment.
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7.发明授权Method and apparatus for implementing binary multiplication using booth type multiplication 失效使用展位类型乘法实现二进制乘法的方法和装置
公开(公告)号：US4972362A
公开(公告)日：1990-11-20
申请号：US209156
申请日：1988-06-17
CPC分类号： G06F7/5318 , G06F7/483 , G06F7/4876 , G06F7/5338 , G06F7/544 , G06F2207/3884 , G06F2207/3896 , G06F2207/5442
摘要： In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results.
摘要翻译： 在高速二进制乘法器电路中，被乘数被分割成一系列8位片，并将乘法器修改为Booth重新编码为3位组。 相应的部分乘积项在小进位存储加法器单元的规则阵列中减小。 CSA阵列的迭代使用提供了百分之七十的芯片面积或常规实现的加法器数量。 该乘法器由内部流水线驱动，由一个对用户透明的快速，两相内部时钟驱动。 内部时钟停止并在加载新的操作数和指令数据时重新启动，以将内部时钟同步到系统时钟。 本发明的其它方面包括用于指数计算的高速绝对值减法电路和浮点结果的归一化。
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公开(公告)号：US5485199A
公开(公告)日：1996-01-16
申请号：US277054
申请日：1994-07-19
申请人： Bob Elkind , Gilbert A. Hoffman
发明人： Bob Elkind , Gilbert A. Hoffman
CPC分类号： G01R13/345 , G01R31/2825 , H04N17/00
摘要： A digital audio waveform display is presented on a digital video waveform display instrument using the video waveform display circuitry. A decoder extracts embedded digital audio data from a digital video signal. The digital audio data is stored in a buffer memory. N digital audio data words, corresponding to N samples of the video data representing a video line for display, are read from the buffer memory at a video sample rate and input to the video waveform display circuitry. The video waveform display circuitry includes a digital to analog converter operating at the video sample rate and an analog video reconstruction filter which provides amplitude values for a swept display device.
摘要翻译： 使用视频波形显示电路在数字视频波形显示仪器上呈现数字音频波形显示。 解码器从数字视频信号中提取嵌入式数字音频数据。 数字音频数据存储在缓冲存储器中。 对应于表示用于显示的视频线的视频数据的N个样本的N个数字音频数据字以视频采样率从缓冲存储器读取并输入到视频波形显示电路。 视频波形显示电路包括以视频采样率工作的数模转换器和模拟视频重构滤波器，该滤波器为扫频显示器件提供振幅值。
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