公开(公告)号：US20120065604A1

公开(公告)日：2012-03-15

申请号：US12880424

申请日：2010-09-13

申请人： Chao-Fu Chang ,  Kent Kuohua Chang

发明人： Chao-Fu Chang ,  Kent Kuohua Chang

IPC分类号： A61L15/64 ,  B29C44/00 ,  A61F13/36 ,  B29C44/04

CPC分类号： B29C44/348 ,  A61F13/36 ,  A61F2013/00221 ,  A61F2013/00463 ,  A61L24/0042 ,  A61L24/0084 ,  A61L24/043 ,  A61L2400/04 ,  C08L67/04

摘要： A degradable hemostatic sponge that can be self-degraded and absorbed by a human body has poly lactic acid as its main material and mixed with a moisture-absorbent material, such as collagen, chitosan, starch and the like, at a specific ratio. Given grinding, mixing and melting steps, the materials using a supercritical fluid as a foaming agent can be used to manufacture the degradable hemostatic sponge having an open-cell microcellular form by a continuous extrusion foaming process. In addition, the present invention also includes a system and a method for manufacturing the degradable hemostatic sponge.

摘要翻译： 可以自身降解并被人体吸收的可降解止血海绵以聚乳酸为主要原料，并以特定的比例与胶原，壳聚糖，淀粉等吸湿材料混合。 考虑到研磨，混合和熔融步骤，使用超临界流体作为发泡剂的材料可用于通过连续挤出发泡方法制造具有开孔细胞微孔形式的可降解止血海绵。 此外，本发明还包括用于制造可降解止血海绵的系统和方法。

公开(公告)号：US06867463B2

公开(公告)日：2005-03-15

申请号：US10248178

申请日：2002-12-24

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L29/788 ,  H01L31/113

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/7887

摘要： A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.

摘要翻译： 提供了一种氮化硅只读存储器结构。 氮化硅只读存储器包括在控制栅极的每一侧上的衬底上的衬底上的源极区和漏极区，控制栅极和衬底之间的电荷捕获层和沟道层 在电荷俘获层下方的衬底和源极区域和漏极区域之间。 电荷捕获层还包括隔离区域。 隔离区域将电荷捕获层划分为源极电荷俘获块和漏极侧电荷俘获块，从而形成2位结构。

公开(公告)号：US06777742B2

公开(公告)日：2004-08-17

申请号：US10064882

申请日：2002-08-27

申请人： Fuh-cheng Jong ,  Kent Kuohua Chang

发明人： Fuh-cheng Jong ,  Kent Kuohua Chang

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4238 ,  H01L29/792

摘要： A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer. In a programming operation, a portion of the gate structure close to the source region serves as an equivalent source region having an area greater than the drain region so that second bit effect is greatly reduced.

公开(公告)号：US06762467B2

公开(公告)日：2004-07-13

申请号：US10412592

申请日：2003-04-14

申请人： Fuh-Cheng Jong ,  Kent Kuohua Chang

发明人： Fuh-Cheng Jong ,  Kent Kuohua Chang

IPC分类号： H01L29792

CPC分类号： H01L29/7887 ,  H01L29/7923

摘要： A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.

摘要翻译： 用于防止第二位效应的非易失性存储单元包括一对排列成沟道的源极/漏极区域，通道上方的可编程层以及可编程层上方的栅极导体。 存储单元的特征在于可编程层具有基本上大于可编程层与源极/漏极区之间的边界宽度的最大宽度。 可编程层包括插入在两个绝缘体层之间的俘获电介质层，并且俘获电介质优选地包括具有掩埋多晶硅岛的氮化物或氧化物。

公开(公告)号：US06737324B2

公开(公告)日：2004-05-18

申请号：US10064561

申请日：2002-07-26

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L21336

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/665

摘要： A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewalls of the gate structure. Thereafter, an elevated layer is formed on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.

摘要翻译： 描述了制造半导体器件的升高的源/漏的方法。 在衬底上形成栅极结构，然后在栅极结构旁边的衬底中形成具有浅结的源极/漏极。 在栅极结构的侧壁上形成间隔物。 此后，在栅极结构和源极/漏极上形成有一个浅结的升高层，其中形成在源极/漏极上的升高层用作升高的源极/漏极层。

公开(公告)号：US06720613B1

公开(公告)日：2004-04-13

申请号：US10248374

申请日：2003-01-15

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7887

摘要： A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.

摘要翻译： 一种制造具有控制栅极，浮置栅极，源极区域，漏极区域和沟道区域的多位闪存的方法。 隔离区域形成在浮动栅极中，以将浮动栅极分隔成多个导电块。 导电块被布置成具有从源极区域延伸到漏极区域的行的阵列。 阵列的每一行都有两个导电块。 在将任何数据写入闪速存储器之前，同一行的导电块下方的沟道区具有相同的阈值电压，而不同行的导电块下的沟道区具有不同的阈值电压。

公开(公告)号：US06624460B1

公开(公告)日：2003-09-23

申请号：US10064764

申请日：2002-08-15

申请人： Weng-Hsing Huang ,  Kent Kuohua Chang

发明人： Weng-Hsing Huang ,  Kent Kuohua Chang

IPC分类号： H01L31119

CPC分类号： H01L21/76897 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10885 ,  Y10S257/905

摘要： A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.

摘要翻译： 描述了一种存储器件及其制造方法。 存储器件包括衬底，掩埋位线，字线结构，电介质层，沟槽中的导线和自对准触点。 掩埋位线位于衬底中，并且字线结构设置在穿过掩埋位线的衬底上。 每个字线结构由字线，栅极氧化物层，覆盖层和间隔物组成。 每个导电线设置在电介质层中并在掩埋位线之上，并且跨越覆盖层。 电介质层设置在字线结构之间和导线之间。 每个自对准触点设置在导电线之间和两个相邻字线之间，以电连接导线和相应的掩埋位线。

公开(公告)号：US06487114B2

公开(公告)日：2002-11-26

申请号：US09795937

申请日：2001-02-28

申请人： Fuh-Cheng Jong ,  Kent Kuohua Chang

发明人： Fuh-Cheng Jong ,  Kent Kuohua Chang

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C16/0475

摘要： A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

公开(公告)号：US06420237B1

公开(公告)日：2002-07-16

申请号：US09682809

申请日：2001-10-22

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/7887

摘要： The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex,x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

摘要翻译： 本发明提供一种双位单元闪存器件及其制造方法。 该方法首先在硅衬底的表面上形成栅氧化层，然后在栅极氧化层上形成多晶锗（Si1-xGex，x = 0.05〜1.0）层。 此后，进行离子注入工艺以在多晶硅锗层中形成至少一个绝缘区域，用于将多晶硅锗层分离成两个隔离的导电区域并形成双位晶胞结构。 然后，在多晶硅锗层上形成电介质层，并进行光蚀刻工艺（PEP）以蚀刻介电层和多晶硅锗层的部分，以形成双位晶胞闪存的浮动栅极。 最后，在浮动栅极上形成控制栅极。

公开(公告)号：US06376309B2

公开(公告)日：2002-04-23

申请号：US09811288

申请日：2001-03-16

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。