公开(公告)号：US6076156A

公开(公告)日：2000-06-13

申请号：US895800

申请日：1997-07-17

申请人： James K. Pickett ,  David S. Christie

发明人： James K. Pickett ,  David S. Christie

IPC分类号： G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30185 ,  G06F9/30145 ,  G06F9/30189

摘要： A microprocessor employs an instruction redefinition register which programmably redefines the operation performed by one or more instructions. Instructions may be added to the instruction set executed by the microprocessor without consuming opcode encodings. One or more new instructions may be mapped to an opcode assigned to a redefinable instruction (e.g. a seldom-used instruction selected during the design of the microprocessor to be redefinable to one or more of the added instructions). A particular application program may select the architecturally defined operation corresponding to the redefinable instruction or one of the operations corresponding to the new operations by coding the instruction redefinition register. In one particular embodiment, the instruction redefinition register is a model specific register (MSR) as defined by the x86 microprocessor architecture. A frequently-used instruction may also be selected as a redefinable instruction for purposes of expanding the microprocessor resources available as operands of that instruction.

摘要翻译： 微处理器采用指令重定义寄存器，其可编程地重新定义由一个或多个指令执行的操作。 可以将指令添加到由微处理器执行的指令集中，而不消耗操作码编码。 可以将一个或多个新指令映射到分配给可重新定义的指令的操作码（例如，在微处理器的设计期间选择的很少使用的指令可重新定义为一个或多个添加的指令）。 特定应用程序可以通过对指令重定义寄存器进行编码来选择对应于可重新定义的指令的结构化定义的操作或与新操作相对应的操作之一。 在一个特定实施例中，指令重新定义寄存器是由x86微处理器架构定义的模型特定寄存器（MSR）。 也可以选择频繁使用的指令作为可重新定义的指令，用于扩展作为该指令的操作数的可用的微处理器资源。

公开(公告)号：US6014739A

公开(公告)日：2000-01-11

申请号：US957900

申请日：1997-10-27

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30145 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30192

摘要： A microprocessor in which a register file of the microprocessor includes a standard register set and an extension register set. The extension register set is available on an instruction-by-instruction basis based on the contents of an extension register key field of the microprocessor instruction. In one embodiment, the instruction set is compliant with an X86 type instruction set in all cases when the extension register key field is not equal to an extension register key value. A microprocessor comprises a register file and an instruction decode circuit. The register file includes a standard register set comprising a plurality of standard registers and an extension register set comprising a plurality of extension registers. The instruction decode circuit is adapted to receive a microprocessor instruction that includes an extension register key field. If the contents of the extension register key field is equal to an extension register key value, then the instruction decode circuit is configured to access the contents of a selected extension register of the extension register set in response to receiving the microprocessor instruction. If, on the other hand, the contents of the extension register key field equal a value other than the extension register key value, then the instruction decode circuit is configured to access the contents of a selected standard register of the standard register set in response to receiving the microprocessor instruction.

摘要翻译： 一种微处理器，其中微处理器的寄存器文件包括标准寄存器组和扩展寄存器组。 基于微处理器指令的扩展寄存器密钥字段的内容，扩展寄存器组可以逐个指令地使用。 在一个实施例中，当扩展注册密钥字段不等于扩展寄存器密钥值时，指令集在所有情况下都符合X86类型的指令集。 微处理器包括寄存器文件和指令解码电路。 寄存器文件包括包括多个标准寄存器的标准寄存器组和包括多个扩展寄存器的扩展寄存器组。 指令解码电路适于接收包括扩展注册密钥字段的微处理器指令。 如果扩展注册密钥字段的内容等于扩展寄存器密钥值，则指令解码电路被配置为响应于接收到微处理器指令来访问所选择的扩展寄存器集合的扩展寄存器的内容。 另一方面，如果扩展注册密钥字段的内容等于除扩展注册密钥值之外的值，则指令解码电路被配置为响应于所述标准寄存器集合的所选标准寄存器的内容来访问 接收微处理器指令。

公开(公告)号：US5819080A

公开(公告)日：1998-10-06

申请号：US582125

申请日：1996-01-02

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30094 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/30185 ,  G06F9/383 ,  G06F9/3846

摘要： A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction. Branch instructions may be scheduled distant from the instruction which sets the condition flags tested by the branch instruction. Numerous instructions may be placed between the two instructions, such that the condition flags may be available at the time the instruction is fetched. The branch instruction may be executed without stalling until the condition flags are available. In another embodiment, the branch prediction unit is configured to predict the direction a branch instruction may take according to a branch prediction scheme. Additionally, upon detection of a segment override prefix byte, the branch prediction unit uses an alternative branch prediction scheme. The alternative branch prediction scheme may be to predict the branch taken if a particular segment register override prefix byte is detected, and to predict the branch not taken if another particular segment register override prefix byte is detected.

摘要翻译： 提供了一种微处理器，其包括分支预测单元，该分支预测单元被配置为根据可能包含在该指令中的分段寄存器覆盖前缀字节来选择由分支指令使用的多组条件标志中的一个。 分支指令可以被调度为远离设置由分支指令测试的条件标志的指令。 可以在两个指令之间放置许多指令，使得条件标志在获取指令时可用。 分支指令可以在不停止的情况下执行，直到条件标志可用。 在另一实施例中，分支预测单元被配置为根据分支预测方案来预测分支指令可以采用的方向。 此外，在检测到段重写前缀字节时，分支预测单元使用替代分支预测方案。 替代分支预测方案可以是预测如果检测到特定分段寄存器覆盖前缀字节所采取的分支，并且如果检测到另一个特定分段寄存器覆盖前缀字节，则预测未采用的分支。

公开(公告)号：US5044676A

公开(公告)日：1991-09-03

申请号：US461384

申请日：1990-01-05

申请人： Kevin Burton ,  David S. Christie

发明人： Kevin Burton ,  David S. Christie

IPC分类号： E21B17/042 ,  E21B17/043 ,  E21B17/08 ,  F16L15/06

CPC分类号： E21B17/085 ,  E21B17/0423 ,  E21B17/043

摘要： A connecting joint for connecting two tubular members together has a pin and a box, each containing conical threaded sections. The pin and the box each has a locking section for locking the pin and box together during make-up. Each locking section has at least one circumferential profile with a crest. The crests are dimensioned so that they interfere with each during make-up. A shoulder locates below each crest. This shoulder is conical and opposite to the taper of the threaded section. The decree of taper of this shoulder is high relative to the longitudinal axis of the pin and box, requiring a large breakout force.

摘要翻译： 用于将两个管状构件连接在一起的连接接头具有一个销和一个箱体，每个都包含锥形螺纹部分。 销和箱每个都有一个锁定部分，用于在化妆期间将销和盒锁定在一起。 每个锁定部分具有至少一个具有顶部的圆周轮廓。 顶部的尺寸设计使它们在化妆时干扰每一个。 肩膀位于每个顶部下方。 该肩部是锥形的，与螺纹部分的锥度相反。 该肩部的锥度方向相对于销和箱的纵向轴线高，需要大的突破力。

公开(公告)号：US09880848B2

公开(公告)日：2018-01-30

申请号：US12814025

申请日：2010-06-11

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/467

摘要： A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

公开(公告)号：US20120159084A1

公开(公告)日：2012-06-21

申请号：US12974171

申请日：2010-12-21

申请人： MARTIN T. POHLACK ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  David S. Christie ,  JaeWoong Chung

发明人： MARTIN T. POHLACK ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  David S. Christie ,  JaeWoong Chung

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3842 ,  G06F9/528 ,  G06F12/0811 ,  G06F12/0815

摘要： A method is provided for identifying a first portion of a computer program for speculative execution by a first processor element. At least one memory object is declared as being protected during the speculative execution. Thereafter, if a first signal is received indicating that the at least one protected memory object is to be accessed by a second processor element, then delivery of the first signal is delayed for a preselected duration of time to potentially allow the speculative execution to complete. The speculative execution of the first portion of the computer program may be aborted in response to receiving the delayed first signal before the speculative execution of the first portion of the computer program has been completed.

摘要翻译： 提供了一种用于识别由第一处理器元件进行推测执行的计算机程序的第一部分的方法。 在推测执行期间，至少有一个内存对象被声明为受保护的。 此后，如果接收到指示所述至少一个被保护的存储器对象将被第二处理器元件访问的第一信号，则第一信号的传送被延迟预选的持续时间以潜在地允许推测执行完成。 计算机程序的第一部分的推测执行可以在计算机程序的第一部分的推测执行已经完成之前响应于接收到延迟的第一信号而中止。

公开(公告)号：US08157015B2

公开(公告)日：2012-04-17

申请号：US12417465

申请日：2009-04-02

申请人： Robert K. Voss ,  David S. Christie ,  Peter Breese

发明人： Robert K. Voss ,  David S. Christie ,  Peter Breese

IPC分类号： E21B43/01

CPC分类号： E21B33/0355 ,  E21B33/0385 ,  E21B33/04

摘要： A subsea wellhead assembly that includes a wellhead housing, a production tree, a tubing hanger adapted to land in the wellhead assembly inside the wellhead housing, and a bore formed through the production tree having an inner diameter greater than the tubing hanger outer diameter. A hanger adapter may be included having an annular body disposed on the tubing hanger upper surface and a flange member projecting radially outward from the annular body.

摘要翻译： 一种海底井口组件，其包括井口壳体，生产树，适于落入井口壳体内的井口组件中的管道悬挂器，以及通过生产树形成的孔，其内径大于管状悬挂架外径。 可以包括衣架适配器，其具有设置在管衣架上表面上的环形主体和从环形体径向向外突出的凸缘构件。

公开(公告)号：US20100023707A1

公开(公告)日：2010-01-28

申请号：US12510856

申请日：2009-07-28

申请人： Michael P. Hohmuth ,  David S. Christie ,  Stephan Diestelhorst

发明人： Michael P. Hohmuth ,  David S. Christie ,  Stephan Diestelhorst

IPC分类号： G06F12/16

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

摘要： A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

摘要翻译： 公开了一种系统和方法，其中耦合到共享存储器的多个处理器的处理器被配置为根据处理器的第一事务模式开始执行代码段。 所述处理器被配置为对所述代码段内的所述共享存储器执行对所述多个处理器的单原子事务的多个受保护存储器访问操作。 处理器还被配置为在代码段内发起根据处理器的第二事务模式执行代码段的子部分，其中第一和第二事务模式各自与相应的恢复动作相关联，处理器 被配置为响应于检测到中止条件而执行。

公开(公告)号：US20100023706A1

公开(公告)日：2010-01-28

申请号：US12510893

申请日：2009-07-28

申请人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

发明人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

IPC分类号： G06F12/00

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

摘要： A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.

摘要翻译： 公开了一种计算机实现的方法和制造物品，用于使得利用硬件事务存储器的计算机程序能够利用传统的锁来安全地与代码交互。 在共享存储器系统中的多个处理器的处理器上执行的线程可以发起一段代码的事务执行，该部分包括对共享存储器的多个访问操作，包括一个或多个到由锁定保护的位置 。 在执行访问与锁相关联的位置的任何操作之前，线程将作为事务的一部分读取锁的值，并且只有在不保持锁定的情况下才会继续。 如果在事务执行期间锁被另一个线程获取，则处理器检测到该获取，中止事务并尝试重新执行该事务。

公开(公告)号：US20100023703A1

公开(公告)日：2010-01-28

申请号：US12510884

申请日：2009-07-28

申请人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

发明人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

IPC分类号： G06F12/00 ,  G06F12/14

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

摘要： A system and method is disclosed for implementing a hardware transactional memory system capable of executing a speculative section of code containing both protected and unprotected memory access operations. A processor in a multi-processor system is configured to execute a section of code that performs a transaction using shared memory, such that a first subset of memory operations in the section of code is performed atomically with respect to the concurrent execution of the one or more other processors and a second subset of memory operations in the section of code is not. In some embodiments, the section of code includes a plurality of declarator operations, each of which is executable to designate a respective location in the shared memory as protected.

摘要翻译： 公开了一种用于实现能够执行包含受保护和不受保护的存储器访问操作的代码的推测部分的硬件事务存储器系统的系统和方法。 多处理器系统中的处理器被配置为执行使用共享存储器执行事务的代码段，使得代码段中的存储器操作的第一子集相对于一个或多个处理器的并行执行原子地执行 更多的其他处理器和第二部分的内存操作在代码段中不是。 在一些实施例中，代码段包括多个声明符操作，每个声明符操作都可执行以将共享存储器中的相应位置指定为受保护的。