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公开(公告)号：US06572252B1
公开(公告)日：2003-06-03
申请号：US09591085
申请日：2000-06-09
IPC分类号： F21V704
CPC分类号： H01L21/67005
摘要： The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.
摘要翻译： 本发明涉及照射半导体处理系统中的处理室的内部部分。 光纤光源与处理室可操作地相关联以照亮室的内部，以便于观察室的内部。
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52.发明授权公开(公告)号：US06479820B1
公开(公告)日：2002-11-12
申请号：US09557720
申请日：2000-04-25
IPC分类号： G03F730
摘要： In one embodiment, the present invention relates to a method of processing a photoresist on a semiconductor structure, involving the steps of exposing and developing the photoresist; evaluating the exposed and developed photoresist to determine if negative charges exist thereon; contacting the exposed and developed photoresist with a positive ion carrier thereby reducing any negative charges thereon; and evaluating the exposed and developed photoresist with an electron beam. In another embodiment, the present invention relates to a system for processing a patterned photoresist on a semiconductor structure, containing a charge sensor for determining if charges exist on the patterned photoresist and measuring the charges; a means for contacting the patterned photoresist with a positive ion carrier to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned photoresist and the positive ion carrier, temperature of the positive ion carrier, concentration of positive ions in the positive ion carrier, and pressure under which contact between the patterned photoresist and the positive ion carrier occurs; and a device for evaluating the patterned photoresist with an electron beam.
摘要翻译： 在一个实施方案中，本发明涉及一种在半导体结构上处理光致抗蚀剂的方法，包括曝光和显影光致抗蚀剂的步骤; 评估曝光和显影的光致抗蚀剂以确定其上是否存在负电荷; 使曝光和显影的光致抗蚀剂与正离子载体接触，从而减少其上的任何负电荷; 并用电子束评估曝光和显影的光致抗蚀剂。 在另一个实施例中，本发明涉及一种用于处理半导体结构上的图案化光致抗蚀剂的系统，其包含用于确定图案化光致抗蚀剂上是否存在电荷并测量电荷的电荷传感器; 用于使图案化的光致抗蚀剂与正离子载体接触以减少其上的电荷的装置; 控制器，用于设置图案化的光致抗蚀剂和正离子载体之间的接触时间中的至少一个，正离子载体的温度，正离子载体中的正离子的浓度以及图案化的光致抗蚀剂和阳离子的正极之间的接触 发生离子载体; 以及用电子束评估图案化光致抗蚀剂的装置。
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53.发明授权System and method for defect identification and location using an optical indicia device 失效使用光标记设备进行缺陷识别和定位的系统和方法公开(公告)号：US07034930B1
公开(公告)日：2006-04-25
申请号：US09634302
申请日：2000-08-08
IPC分类号： G01N21/88
CPC分类号： G01N21/9501 , G01N21/956
摘要： A measuring system and method are provided for defect identification and location. The system an optical measurement device adapted to view a workpiece along an optical path, and an optical indicia device located in the optical path between the workpiece and the measurement device, which is adapted to provide location information to the system or a user. The location information can be used to correlate defect locations identified in a wafer before and after a process step, as well as between two different wafers. The optical indicia device may further allow the use of field comparison techniques in identifying and locating defects in a blank or unpatterned workpiece. The indicia device may comprise, for example, a transparent member having a grid or other optical indicia patterned thereon, allowing inspection of the workpiece with reference to the optical indicia pattern.
摘要翻译： 提供了一种用于缺陷识别和定位的测量系统和方法。 该系统适于沿着光路观察工件，以及位于工件和测量装置之间的光路中的光学标记装置，其适于向系统或用户提供位置信息。 位置信息可用于将在晶片中识别的缺陷位置与处理步骤之间以及两个不同的晶片之间相关联。 光学标记装置还可以允许使用现场比较技术来识别和定位空白或未图案化的工件中的缺陷。 标记装置可以包括例如具有图案化的网格或其他光学标记的透明构件，允许参考光标记图案检查工件。
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54.发明授权Use of non-lithographic shrink techniques for fabrication/making of imprints masks 失效使用非光刻收缩技术制造/制作印记掩模公开(公告)号：US07159205B1
公开(公告)日：2007-01-02
申请号：US10838830
申请日：2004-05-04
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
IPC分类号： G06F17/50
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , G03F7/40
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.
摘要翻译： 本发明一般涉及光刻系统和方法，更具体地涉及在压印掩模中在图案线形成期间促进改进的临界尺寸（CD）控制和减少线边缘粗糙度（LER）的系统和方法。 本发明的一个方面提供了形成具有大于掩模抗蚀剂中最终期望的CD的特征。 在施加非光刻收缩技术时，LER被减轻并且CD被减小到期望的目标公差内。
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55.发明授权System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化公开(公告)号：US07148142B1
公开(公告)日：2006-12-12
申请号：US10874500
申请日：2004-06-23
IPC分类号： H01L21/44
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译： 提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。 该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。 压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。 当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。 卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。 第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。 电介质蚀刻将图案从转印层转移到电介质层中。 然后，金属填充过程用金属填充介电层的双镶嵌开口。
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公开(公告)号：US06486072B1
公开(公告)日：2002-11-26
申请号：US09709974
申请日：2000-11-10
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/02046
摘要： A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.
摘要翻译： 公开了一种用于便于从基底去除缺陷的系统和方法。 在基板的表面，例如以电离气体的形式施加电荷，以减弱缺陷和基板之间的吸引力。 作为吸引力减弱的结果，可以采用合适的缺陷去除系统来去除缺陷。
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57.发明授权Low cost application of oxide test wafer for defect monitor in photolithography process 失效用于光刻工艺中缺陷监测器的氧化物测试晶片的低成本应用公开(公告)号：US06171737B2
公开(公告)日：2001-01-09
申请号：US09017695
申请日：1998-02-03
IPC分类号： G03F900
CPC分类号： G03F7/7065 , H01L22/20 , H01L22/34
摘要： A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel. An optical review station and scanning electron microscope system are used to review defect and classify defect types. The test wafer can then be reused by cleaning the photolithographic pattern by removing the photoresist, and then removing polymer particles adhering to the oxide layer following removal of the photoresist.
摘要翻译： 在亚微米集成电路制造环境中用于检测光刻工艺中的缺陷的低成本技术将使用可重复使用的测试晶片与在线处理相结合，以使用模式比较器系统来监测缺陷。 使用规定的光刻制造工艺对具有覆盖在硅衬底上并具有与用于光刻的曝光波长的最小反射率相对应的厚度的可重复使用的测试晶片图案化以根据规定的设计产品规则形成重复图案。 使用具有与通过光刻工艺开发的产品相似的设计规则的具有重复图案阵列的掩模版形成图案。 然后使用基于图像的检查技术来检查图案化的测试晶片，其中图像具有每像素优选0.25微米的高分辨率像素。 光学检查站和扫描电子显微镜系统用于检查缺陷并分类缺陷类型。 然后可以通过除去光致抗蚀剂来清洁光刻图案，然后在去除光致抗蚀剂之后去除粘附到氧化物层上的聚合物颗粒，来重新使用测试晶片。
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公开(公告)号：US07591902B2
公开(公告)日：2009-09-22
申请号：US11615080
申请日：2006-12-22
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael T. Templeton
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译： 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。
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59.发明授权Apparatus and method for reducing defects in a semiconductor lithographic process 有权用于减少半导体光刻工艺中的缺陷的装置和方法公开(公告)号：US06222936B1
公开(公告)日：2001-04-24
申请号：US09394871
申请日：1999-09-13
IPC分类号： G06K900
CPC分类号： G03F7/70616 , G03F7/7065
摘要： An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
摘要翻译： 用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案，以模拟半导体产品的实际处理条件。 然后使用晶片检查系统检查抗蚀剂图案。 在线低电压扫描电子显微镜（SEM）系统评估和分类缺陷类型，实现替代处理规范的生成。 然后可以通过在不同晶片上形成图案来测试替代处理规范，然后进行分裂式测试以分析不同晶片上的图案，以与现有的光刻工艺和生产资格进行比较。
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公开(公告)号：US5985497A
公开(公告)日：1999-11-16
申请号：US17678
申请日：1998-02-03
CPC分类号： G03F7/70616 , G03F7/7065
摘要： An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.
摘要翻译： 用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案，以模拟半导体产品的实际处理条件。 然后使用晶片检查系统检查抗蚀剂图案。 在线低电压扫描电子显微镜（SEM）系统评估和分类缺陷类型，实现替代处理规范的生成。 然后可以通过在不同晶片上形成图案来测试替代处理规范，然后进行分裂式测试以分析不同晶片上的图案，以与现有的光刻工艺和生产资格进行比较。
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