利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.028 秒)

    Storage device backplane and identification circuit
    51.
    发明授权
    Storage device backplane and identification circuit 有权
    存储设备背板和识别电路

    公开(公告)号：US08045336B2

    公开(公告)日：2011-10-25

    申请号：US12025505

    申请日：2008-02-04

    申请人： Lan Huang ,  Shih-Hao Liu

    发明人： Lan Huang ,  Shih-Hao Liu

    IPC分类号： H05K1/11 ,  H05K1/14

    CPC分类号： G06F13/409 ,  G06F13/4247

    摘要： A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.

    摘要翻译： 提供了存储设备背板和用于识别存储设备背板的使用情况的识别电路。 存储设备背板具有第一连接接口和第二连接接口，用于作为支撑母板的第一背板或级联到第一背板的第二背板或支撑母板的子板的第一背板。 第一和第二背板具有相同的存储设备背板结构。 如果存储设备背板用作第一背板，则第一背板的第一连接接口耦合到主板或其母板; 如果存储设备背板用作第二背板，则第二背板的第一连接接口耦合到第一背板的第二连接接口。 识别电路识别存储设备背板的使用情况，并显示相应的正确指示器编号。

    Core voltage controlling apparatus
    53.
    发明授权
    Core voltage controlling apparatus 有权
    核心电压控制装置

    公开(公告)号：US07853810B2

    公开(公告)日：2010-12-14

    申请号：US11960178

    申请日：2007-12-19

    申请人： Lan Huang ,  Shih-Hao Liu

    发明人： Lan Huang ,  Shih-Hao Liu

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26

    摘要： A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state.

    摘要翻译： 提供一种适用于中央处理单元（CPU）的核心电压控制装置。 该装置包括电平转换单元，延时单元和逻辑单元。 电平移位单元的输入端子接收并移位第一电压信号，并且输出端子产生其中第一电压信号指示通电稳定状态的第二电压信号，并且第二电压信号指示第 核心电压。 时间延迟单元延迟第二电压信号以产生第三电压信号。 逻辑单元耦合到时间延迟单元，用于对由电源发送的第三电压和第四电压信号进行逻辑运算，并产生用于控制核心电压发生器的第五电压信号，以提供核心电压 CPU，否则，第四电压信号表示电源状态。

    Memory reset apparatus
    55.
    发明授权
    Memory reset apparatus 失效
    存储器复位装置

    公开(公告)号：US07616039B2

    公开(公告)日：2009-11-10

    申请号：US11970962

    申请日：2008-01-08

    申请人： Lan Huang ,  Shih-Hao Liu

    发明人： Lan Huang ,  Shih-Hao Liu

    IPC分类号： H03K3/02 ,  G06F13/00

    CPC分类号： G11C5/063 ,  H03K17/22

    摘要： A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.

    摘要翻译： 提供了包括第一反向电路，逻辑电路和多个第二反向电路的存储器复位装置。 第一反向电路接收由北桥产生的控制信号，并产生第一信号，其中控制信号控制多个存储器的复位。 逻辑电路执行第一信号和指示信号的逻辑运算，并产生第二信号，其中指示信号指示计算机系统的每个部件完全通电。 多个第二反向电路分别耦合在逻辑电路和存储器之间。 第二反向电路与第二信号反相并分别产生多个复位信号给存储器，从而复位存储器。

    SYSTEM AND METHOD FOR ENABLING EFFICIENT SMALL WRITES TO WORM STORAGE
    57.
    发明申请
    SYSTEM AND METHOD FOR ENABLING EFFICIENT SMALL WRITES TO WORM STORAGE 有权
    用于实现有效的小写入到存储的系统和方法

    公开(公告)号：US20090141619A1

    公开(公告)日：2009-06-04

    申请号：US12334280

    申请日：2008-12-12

    申请人： Windsor Wee Sun Hsu ,  Lan Huang ,  Michael Anthony Ko ,  Shauchi Ong

    发明人： Windsor Wee Sun Hsu ,  Lan Huang ,  Michael Anthony Ko ,  Shauchi Ong

    IPC分类号： G11B7/00

    CPC分类号： G11B27/3027 ,  G11B2020/1232 ,  G11B2020/1292 ,  G11B2220/218 ,  G11B2220/2516

    摘要： According to the present invention, there is provided a method of providing a WORM storage system, the method including a sector-append capability. The method includes receiving data to be written to a WORM storage system. In addition, the method includes identifying a target sector at which the data is to be written. Also, the method includes determining if the received data can be added to the target sector. Moreover, the method includes adding the received data to the target sector if it is determined that the received data can be added to the target sector.

    摘要翻译： 根据本发明，提供了一种提供WORM存储系统的方法，该方法包括扇区附加能力。 该方法包括接收要写入WORM存储系统的数据。 此外，该方法包括识别要写入数据的目标扇区。 此外，该方法包括确定所接收的数据是否可以被添加到目标扇区。 此外，如果确定可以将接收的数据添加到目标扇区，则该方法包括将接收到的数据添加到目标扇区。

    SYSTEM AND METHOD FOR EFFICIENT RULE UPDATES IN POLICY BASED DATA MANAGEMENT
    58.
    发明申请
    SYSTEM AND METHOD FOR EFFICIENT RULE UPDATES IN POLICY BASED DATA MANAGEMENT 审中-公开
    基于政策数据管理的有效规则更新的系统和方法

    公开(公告)号：US20090077133A1

    公开(公告)日：2009-03-19

    申请号：US11856475

    申请日：2007-09-17

    申请人： Windsor Hsu ,  Lan Huang

    发明人： Windsor Hsu ,  Lan Huang

    IPC分类号： G06F17/30

    CPC分类号： G06F16/122

    摘要： A method, system, and computer program product is provided for efficient policy rule update in a data management system. A policy rule is stored along with the attributes of a data object when the application of the policy rule results in action taken on the data object. A stored policy rule, called an effective policy rule, is subsequently used to restrict the number of data objects examined when a policy rule is added, deleted, modified, or otherwise updated.

    摘要翻译： 提供了一种在数据管理系统中有效的策略规则更新的方法，系统和计算机程序产品。 当策略规则的应用导致对数据对象采取的操作时，策略规则与数据对象的属性一起存储。 随后使用存储的策略规则（称为有效策略规则）来限制在添加，删除，修改或更新策略规则时检查的数据对象的数量。

    Hydration control of cementitious systems
    59.
    发明授权
    Hydration control of cementitious systems 失效
    水泥系统的水化控制

    公开(公告)号：US5634972A

    公开(公告)日：1997-06-03

    申请号：US596901

    申请日：1996-03-13

    申请人： John T. Pacanovsky ,  Lan Huang ,  Frank T. Gay ,  Samy M. Shendy

    发明人： John T. Pacanovsky ,  Lan Huang ,  Frank T. Gay ,  Samy M. Shendy

    IPC分类号： B28C7/00 ,  C04B24/06 ,  C04B28/02 ,  C04B40/06 ,  C04B24/04

    CPC分类号： C04B24/06 ,  C04B28/02 ,  C04B40/0658 ,  C04B2103/12 ,  C04B2103/22 ,  C04B2111/00155 ,  Y02W30/94

    摘要： A method of controlling the hydration of a cementitious composition comprising the steps of:i) providing a cementitious composition containing an amount of a neutralized salt of an alpha-monohydroxy carboxylic acid effective to retard the cementitious composition, said carboxylic acid containing two or more carboxylic acid groups, and subsequently,ii) adding an additional amount of said neutralized salt of an alpha monohydroxy carboxylic acid or a second neutralized salt of an alpha monohydroxy carboxylic acid in an amount sufficient to activate hydration of the retarded cementitious composition, said cementitious composition comprising hydraulic binder and water.

    摘要翻译： 一种控制水泥组合物水化的方法，包括以下步骤：i）提供含有一定量的中和的α-单羟基羧酸盐的水泥组合物，其有效地延缓胶结组合物，所述羧酸含有两个或更多个羧酸 酸基团，随后，ii）加入额外量的α单羟基羧酸的所述中和盐或α单羟基羧酸的第二中和盐，其量足以活化延迟水泥质组合物的水合，所述胶结组合物包含 水力粘合剂和水。