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51.发明授权Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上公开(公告)号：US07460003B2
公开(公告)日：2008-12-02
申请号：US11372387
申请日：2006-03-09
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。
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52.发明授权Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权具有不同晶体取向的共面绝缘体上硅（SOI）区域及其制造方法公开(公告)号：US07439108B2
公开(公告)日：2008-10-21
申请号：US11155030
申请日：2005-06-16
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了半导体器件制造的第一种方法。 第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。 第一，第二和第三SOI区域是共面的。 提供了许多其他方面。
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公开(公告)号：US20080217614A1
公开(公告)日：2008-09-11
申请号：US12124575
申请日：2008-05-21
IPC分类号： H01L23/58
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译： 公开了用于控制电迁移的系统和方法，并减少其有害影响。 实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。 在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。 在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。 在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。 提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。
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公开(公告)号：US20080157261A1
公开(公告)日：2008-07-03
申请号：US12049258
申请日：2008-03-14
IPC分类号： H01L27/12
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。
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55.发明授权Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures 有权具有封装的栅电极的半导体FinFET结构和用于形成这种半导体FinFET结构的方法公开(公告)号：US07384838B2
公开(公告)日：2008-06-10
申请号：US11225654
申请日：2005-09-13
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.
摘要翻译： 其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。 栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。 栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。
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公开(公告)号：US07339390B2
公开(公告)日：2008-03-04
申请号：US11140765
申请日：2005-05-31
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
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公开(公告)号：US06828232B2
公开(公告)日：2004-12-07
申请号：US10705116
申请日：2003-11-10
IPC分类号： H01L214763
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
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58.发明授权Hierarchical power supply noise monitoring device and system for very large scale integrated circuits 有权用于大型集成电路的分层电源噪声监测装置和系统公开(公告)号：US06823293B2
公开(公告)日：2004-11-23
申请号：US10334312
申请日：2002-12-31
申请人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
发明人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G06F1500
CPC分类号： G01R31/3004 , G01R31/31721
摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.
摘要翻译： 一种用于大规模集成电路的分层电源噪声监测装置和系统。 噪声监测装置是片上制造的，以测量芯片上的噪声。 噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。 噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。
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公开(公告)号：US06552378B1
公开(公告)日：2003-04-22
申请号：US09385931
申请日：1999-08-30
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10832 , H01L27/10873
摘要： A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.
摘要翻译： 本文公开了一种具有4.5F2或更小尺寸的半导体存储器单元的制造结构和方法，其中F是最小光刻尺寸。 半导体存储单元包括形成在沟槽中的存储电容器，形成在基本上电隔离的台面区域中的转移装置，该台面区域延伸在沟槽的外周边的大致圆弧上，将传输装置导电地连接到存储电容器 ，其中所述传送装置具有位于从所述掩埋带移除的所述弧的位置处的受控传导通道。
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60.发明授权N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法公开(公告)号：US06433397B1
公开(公告)日：2002-08-13
申请号：US09488515
申请日：2000-01-21
IPC分类号： H01L27085
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在基板上的升压栅叠层，具有通过低浓度N型注入形成的源极和漏极，以及N- 驱动器耦合到升压栅极堆叠。
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