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    DRAM cell with transfer device extending along perimeter of trench storage capacitor
    1.
    发明授权
    DRAM cell with transfer device extending along perimeter of trench storage capacitor 失效
    具有转移装置的DRAM单元沿沟槽存储电容器的周边延伸

    公开(公告)号：US6037620A

    公开(公告)日：2000-03-14

    申请号：US93904

    申请日：1998-06-08

    申请人： Heinz Hoenigschmid ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Heinz Hoenigschmid ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10873

    摘要： A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap. Also disclosed herein are methods of forming a semiconductor memory cell and of forming groups of semiconductor memory cells. A method of forming a semiconductor memory cell includes the steps of forming a storage capacitor in a deep trench etched into a substrate including a monocrystalline semiconductor; forming a shallow trench isolation (STI) region at least partially overlaying the deep trench; forming and outdiffusing a strap in a sidewall of the deep trench; forming first spacers on exterior surfaces of the STI region and deep trench; etching, selective to the monocrystalline semiconductor; removing the first spacers to expose a mesa region of monocrystalline semiconductor located on exterior sidewalls of the deep trench and STI region and conductively connected to the strap; adjusting dopant concentrations in at least a portion of the mesa region to form a channel region and source/drain regions; forming a gate dielectric over at least the channel region; depositing a gate conductor over the channel region; and forming a bitline contact to a first of the source/drain regions.

    摘要翻译： 本文公开了一种具有4.5F2或更小尺寸的半导体存储器单元的制造结构和方法，其中F是最小光刻尺寸。 半导体存储单元包括形成在沟槽中的存储电容器，形成在基本上电隔离的台面区域中的转移装置，该台面区域延伸在沟槽的外周边的大致圆弧上，将传输装置导电地连接到存储电容器 ，其中所述传送装置具有位于从所述掩埋带移除的所述弧的位置处的受控传导通道。 本文还公开了形成半导体存储单元和形成半导体存储单元组的方法。 形成半导体存储单元的方法包括以下步骤：在蚀刻到包括单晶半导体的衬底的深沟槽中形成存储电容器; 形成至少部分覆盖所述深沟槽的浅沟槽隔离（STI）区域; 在深沟槽的侧壁中形成和扩散带; 在STI区域和深沟槽的外表面上形成第一间隔物; 蚀刻，对单晶半导体有选择性; 去除第一间隔物以暴露位于深沟槽和STI区域的外侧壁上的单晶半导体的台面区域，并导电连接到带子; 在所述台面区域的至少一部分中调整掺杂剂浓度以形成沟道区域和源极/漏极区域; 在至少沟道区上形成栅极电介质; 在沟道区域上沉积栅极导体; 以及形成与源极/漏极区域中的第一个的位线接触。

    Ultra compact DRAM cell and method of making
    2.
    发明授权
    Ultra compact DRAM cell and method of making 失效
    超小型DRAM单元及其制造方法

    公开(公告)号：US06552378B1

    公开(公告)日：2003-04-22

    申请号：US09385931

    申请日：1999-08-30

    申请人： Heinz Hoenigschmid ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Heinz Hoenigschmid ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L27/10873

    摘要： A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transfer device formed in a substantially electrically isolated mesa region extending over a substantial arc of the outer perimeter of the trench, a buried strap which conductively connects the transfer device to the storage capacitor, wherein the transfer device has a controlled conduction channel located at a position of the arc removed from the buried strap.

    摘要翻译： 本文公开了一种具有4.5F2或更小尺寸的半导体存储器单元的制造结构和方法，其中F是最小光刻尺寸。 半导体存储单元包括形成在沟槽中的存储电容器，形成在基本上电隔离的台面区域中的转移装置，该台面区域延伸在沟槽的外周边的大致圆弧上，将传输装置导电地连接到存储电容器 ，其中所述传送装置具有位于从所述掩埋带移除的所述弧的位置处的受控传导通道。

    Reference for MRAM cell
    5.
    发明授权
    Reference for MRAM cell 有权
    MRAM细胞参考

    公开(公告)号：US06426907B1

    公开(公告)日：2002-07-30

    申请号：US09836817

    申请日：2001-04-17

    申请人： Heinz Hoenigschmid

    发明人： Heinz Hoenigschmid

    IPC分类号： G11C700

    CPC分类号： G11C11/15

    摘要： A reference circuit (132) for an MRAM array, including logic “1” reference MRAM cells (MR1a) and (MR1b) coupled in parallel with logic “0” reference MRAM cells (MR0a) and (MR0b) The reference current (Iref)is coupled to a measurement resistor (Rm4) of a sense amplifier (130) which is adapted to determine the logic state of an unknown memory cell MCu.

    摘要翻译： 用于MRAM阵列的参考电路（132）包括与逻辑“0”参考MRAM单元（MR0a）和（MR0b）并联耦合的逻辑“1”参考MRAM单元（MR1a）和（MR1b）。参考电流（Iref） 耦合到读出放大器（130）的测量电阻器（Rm4），其适于确定未知存储器单元MCu的逻辑状态。

    Dynamic random access memory arrays and methods therefor
    6.
    发明授权
    Dynamic random access memory arrays and methods therefor 失效
    动态随机存取存储器阵列及其方法

    公开(公告)号：US5821592A

    公开(公告)日：1998-10-13

    申请号：US884853

    申请日：1997-06-30

    申请人： Heinz Hoenigschmid ,  John DeBrosse

    发明人： Heinz Hoenigschmid ,  John DeBrosse

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10805 ,  H01L27/10882 ,  Y10S257/905 ,  Y10S257/907

    摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.

    摘要翻译： 一种具有存储器单元阵列的动态随机存取存储器阵列。 该阵列的单个单元可由多个字线和多个位线寻址。 存储单元被布置在阵列的有效区域中。 存储单元的阵列包括第一条存储单元。 动态随机存取存储器阵列包括下金属层和设置在下金属层上方的上金属层。 动态随机存取存储器阵列还包括设置在下金属层和上金属层之间的电介质层。 还包括多个位线的第一位线，其包括实现在下金属层中的下金属第一位线部分。 下金属第一位线部分耦合到第一条存储器单元的第一多个存储单元。 第一位线还包括实现在上金属层中的上金属第一位线部分。 上金属第一位线部分通过介电层的第一接触耦合到下部第一金属位线部分。 第一触点设置在有效区域之上。

    FB DRAM memory with state memory
    8.
    发明授权
    FB DRAM memory with state memory 有权
    FB DRAM内存带状态存储器

    公开(公告)号：US07848134B2

    公开(公告)日：2010-12-07

    申请号：US12178407

    申请日：2008-07-23

    申请人： Milena Ivanov ,  Heinz Hoenigschmid ,  Stefan Dietrich ,  Michael Markert

    发明人： Milena Ivanov ,  Heinz Hoenigschmid ,  Stefan Dietrich ,  Michael Markert

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4091 ,  G11C11/404 ,  G11C2211/4016

    摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

    摘要翻译： 公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。 存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。 存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。 存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

    Memory device
    10.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US06624461B1

    公开(公告)日：2003-09-23

    申请号：US10089910

    申请日：2002-06-27

    申请人： Heinz Hoenigschmid ,  Georg Braun

    发明人： Heinz Hoenigschmid ,  Georg Braun

    IPC分类号： H01L27108

    CPC分类号： H01L27/10885 ,  G11C5/10 ,  H01L27/10811 ,  H01L27/10814

    摘要： The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and driven via word and bit lines. This memory device comprises two metallized sheets through which the bit line is led and between which the memory cell stacked capacitor is arranged.

    摘要翻译： 本发明涉及包括多个存储器单元的存储器件，每个单元包括至少一个选择晶体管和一个堆叠电容器，并通过字和位线驱动。 该存储器件包括两个金属化片，位线被引导通过该金属化片，布置有存储单元堆叠电容器之间。