公开(公告)号：US20140379836A1

公开(公告)日：2014-12-25

申请号：US13925868

申请日：2013-06-25

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Omer Zilberboim ,  Ofer Hayut ,  Yaron Haviv ,  Liron Mula ,  Noam Bloch ,  Nir Getter ,  Ariel Shachar

IPC: G06F3/06

CPC classification number: G06F11/1076 ,  G06F2211/1028 ,  H04L67/1097

Abstract: A network interface includes a host interface for communicating with a node, and circuitry which is configured to communicate with one or more other nodes over a communication network so as to carry out, jointly with one or more other nodes, a redundant storage operation that includes a redundancy calculation, including performing the redundancy calculation on behalf of the node.

Abstract translation: 网络接口包括用于与节点进行通信的主机接口，以及被配置为通过通信网络与一个或多个其他节点进行通信以便与一个或多个其他节点一起执行冗余存储操作的电路，所述冗余存储操作包括 冗余计算，包括代表节点执行冗余计算。

公开(公告)号：US12231343B2

公开(公告)日：2025-02-18

申请号：US17902936

申请日：2022-09-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Lion Levi ,  Yuval Shpigelman

IPC: H04L47/26 ,  H04L47/10 ,  H04L47/2425 ,  H04L47/30 ,  H04L47/62

Abstract: A network element includes a transmit-queue for transmitting packets from at least two sources, each source having a predefined priority level, to a headroom buffer in a peer network element. Flow-control circuitry receives from the peer network element signaling that indicates a number of credits for transmitting packets to the peer network element, manages a current number of credits available for transmission from the transmit-queue, responsive to the signaling, selects a threshold priority based on the current number of credits for the transmit-queue; and transmits packets associated with data sources of the transmit-queue that are higher in priority than the threshold priority, and refrain from transmitting other packets associated with the transmit-queue.

公开(公告)号：US20250039109A1

公开(公告)日：2025-01-30

申请号：US18225562

申请日：2023-07-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eran Gil Beracha ,  Liron Mula ,  Barak Gafni ,  Gil Levy ,  Aviv Kfir

IPC: H04L49/9047 ,  H04L47/125 ,  H04L47/62

Abstract: A system, a computing system, and a switch are provided. In one example, a system for routing data to one of a plurality of queues comprises a processor to poll a depth of one or more queues of the plurality of queues, determine a weight for each polled queue based on the depth of each polled queue, and route data received via a port to a first queue of the plurality of queues based on the determined weight for each polled queue.

公开(公告)号：US20250038871A1

公开(公告)日：2025-01-30

申请号：US18914324

申请日：2024-10-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Liron Mula ,  Elad Mentovich ,  Paraskevas Bakopoulos ,  Eitan Zahavi ,  Sagi Kuks

IPC: H04J3/06 ,  H04Q11/00

Abstract: A system includes multiple processors to communicate with one another at predefined time slots. A given processor among the processors is to (i) hold a predetermined schedule plan that specifies which of the other processors in the system are accessible to the given processor at which of the time slots, the predetermined schedule plan having been determined before receiving data for transmission from the given processors to the other processors, (ii) queue data that is destined to one or more of the other processors, and (iii) transmit the queued data in accordance with the predetermined schedule plan.

公开(公告)号：US20240373379A1

公开(公告)日：2024-11-07

申请号：US18225525

申请日：2023-07-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

IPC: H04W56/00

Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

公开(公告)号：US20240373378A1

公开(公告)日：2024-11-07

申请号：US18143509

申请日：2023-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ran Ravid ,  Guy Lederman ,  Liron Mula ,  Eitan Zahavi ,  Peter Paneah

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.

公开(公告)号：US12120035B2

公开(公告)日：2024-10-15

申请号：US17844362

申请日：2022-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Aviv Kfir ,  Miri Shtaif ,  Eran Gil Beracha

IPC: H04L47/56 ,  H04L43/0852 ,  H04L47/625

CPC classification number: H04L47/56 ,  H04L43/0852 ,  H04L47/625

Abstract: A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.

公开(公告)号：US12008147B2

公开(公告)日：2024-06-11

申请号：US17520093

申请日：2021-11-05

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Dimitris Syrivelis ,  Liron Mula ,  Aviad Levy ,  Elad Mentovich

IPC: G06F21/72 ,  H04L9/08 ,  H04L9/40 ,  G06F21/85

CPC classification number: G06F21/72 ,  H04L9/0852 ,  H04L63/0435 ,  H04L63/061 ,  G06F21/85

Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.

公开(公告)号：US11991159B2

公开(公告)日：2024-05-21

申请号：US17568582

申请日：2022-01-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Barak Gafni ,  Liron Mula

IPC: H04L9/40 ,  H04L12/46

CPC classification number: H04L63/0485 ,  H04L63/162 ,  H04L63/164 ,  H04L12/4633 ,  H04L63/0428

Abstract: Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device includes multiple ports, a network processing element, a programmable path-selection circuit, and a security IC. The programmable path-selection circuit is configured to operate in a first mode in which first outgoing packets are routed to the security integrated circuit to be encrypted before sending on one of the ports, and first incoming packets, received on one of the ports, are routed to the security integrated circuit to be decrypted. The programmable path-selection circuit is configured to operate in a second mode in which second incoming packets are routed to the security integrated circuit to be encrypted before processing by the network processing element and route second outgoing packets to the security integrated circuit to be decrypted after processing by the network processing element.

公开(公告)号：US11907754B2

公开(公告)日：2024-02-20

申请号：US17549949

申请日：2021-12-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Liron Mula ,  Natan Manevich

IPC: G06F9/48 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F9/4825 ,  G06F1/08 ,  G06F9/485 ,  G06F13/1689

Abstract: In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.