公开(公告)号：US20200327057A1

公开(公告)日：2020-10-15

申请号：US16912434

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F12/0806 ,  H04L5/00

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US20200272567A1

公开(公告)日：2020-08-27

申请号：US16778151

申请日：2020-01-31

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: G06F12/0862 ,  G06F13/16 ,  H01L25/065 ,  G11C11/4093

Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

公开(公告)号：US20200162066A1

公开(公告)日：2020-05-21

申请号：US16198493

申请日：2018-11-21

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans

IPC: H03K5/156 ,  G11C11/4076 ,  G11C29/50

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

公开(公告)号：US10649687B2

公开(公告)日：2020-05-12

申请号：US16113854

申请日：2018-08-27

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/02

Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.

公开(公告)号：US10481819B2

公开(公告)日：2019-11-19

申请号：US15798083

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US20190341085A1

公开(公告)日：2019-11-07

申请号：US16513431

申请日：2019-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US10381050B2

公开(公告)日：2019-08-13

申请号：US15855849

申请日：2017-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C8/00 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US10372330B1

公开(公告)日：2019-08-06

申请号：US16022421

申请日：2018-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Shunichi Saito

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/10

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

公开(公告)号：US20190129635A1

公开(公告)日：2019-05-02

申请号：US15798083

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/1045 ,  G11C2207/2272

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US10090836B1

公开(公告)日：2018-10-02

申请号：US15901737

申请日：2018-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans

IPC: H03K19/00 ,  H03K19/003 ,  G11C29/02 ,  G11C11/4094 ,  H03K19/0175 ,  G11C11/4093

Abstract: A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes.