公开(公告)号：US20230058645A1

公开(公告)日：2023-02-23

申请号：US17404875

申请日：2021-08-17

Applicant: Micron Technology, Inc.

Inventor： Sandeep Reddy Kadasani ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Niccolo' Righetti ,  Chi Ming Chu

IPC: G06F3/06

Abstract: A read operation is performed on a memory device in accordance with a pass-through voltage setting that defines a pass-through voltage applied to one or more cells of the memory device during read operations. A number of zero bits read from the memory device based on the read operation are counted and compared with a threshold value. Based on the number of zero bits exceeding the threshold value, the pass-through voltage is increased by adjusting the pass-through voltage setting.

公开(公告)号：US20220350520A1

公开(公告)日：2022-11-03

申请号：US17867489

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, JR. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C29/50

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

公开(公告)号：US20220308778A1

公开(公告)日：2022-09-29

申请号：US17212437

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

公开(公告)号：US11385819B2

公开(公告)日：2022-07-12

申请号：US16995682

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

公开(公告)号：US20220197771A1

公开(公告)日：2022-06-23

申请号：US17691957

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, JR. ,  Niccolo' Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/30 ,  G11C5/14 ,  G11C16/34

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

公开(公告)号：US20220189571A1

公开(公告)日：2022-06-16

申请号：US17122758

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, JR. ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Kishore K. Muchherla ,  Gil Golov ,  Todd A. Marquart ,  Jiangang Wu ,  Niccolo' Righetti ,  Ashutosh Malshe

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30

Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.

公开(公告)号：US20220066898A1

公开(公告)日：2022-03-03

申请号：US17005114

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Todd A. Marquart ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Kishore K. Muchherla ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/14 ,  G06F11/07 ,  G06F11/32 ,  G06F1/30

Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.

公开(公告)号：US20220066677A1

公开(公告)日：2022-03-03

申请号：US17001729

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, JR. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

公开(公告)号：US11189355B1

公开(公告)日：2021-11-30

申请号：US17001745

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/32 ,  G11C16/14

Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.