公开(公告)号：US20240241736A1

公开(公告)日：2024-07-18

申请号：US18621898

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F9/448 ,  G06F13/12 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis. The system also includes a secondary device coupled to the primary device, wherein the secondary device comprises a second plurality of configurable elements configured to analyze at least a portion of second data received from the primary device as a second analysis and to output a result of the second analysis, wherein the primary device

公开(公告)号：US11947979B2

公开(公告)日：2024-04-02

申请号：US17736399

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F13/16 ,  G06F9/448 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4498 ,  G06F13/126 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/38 ,  G06F13/4282

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

公开(公告)号：US11816493B2

公开(公告)日：2023-11-14

申请号：US16951616

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Paul Glendenning ,  Jeffery M. Tanner ,  Michael C. Leventhal ,  Harold B Noyes

IPC: G06F9/448 ,  G06F8/30

CPC classification number: G06F9/4498 ,  G06F8/31

Abstract: A markup language is provided. The markup language describes the composition of automata networks. For example, the markup language uses elements that represent automata processing resources. These resources may include at least one of a state transition element, a counter element, and a Boolean element as respective automata processing resources.

公开(公告)号：US20210232630A1

公开(公告)日：2021-07-29

申请号：US17228212

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Paul Glendenning ,  Michael C. Leventhal ,  Paul Dlugosch ,  Harold B. Noyes

IPC: G06F16/901 ,  G06F16/904 ,  G06N3/00 ,  G06F8/41 ,  G06F8/34

Abstract: The Automata Processor Workbench (AP Workbench) is an application for creating and editing designs of AP networks (e.g., one or more portions of the state machine engine, one or more portions of the FSM lattice, or the like) based on, for example, an Automata Network Markup Language (ANML). For instance, the application may include a tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions include instructions to represent an automata network as a graph.

公开(公告)号：US10949290B2

公开(公告)日：2021-03-16

申请号：US16547241

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US20210073004A1

公开(公告)日：2021-03-11

申请号：US16951616

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Paul Glendenning ,  Jeffrey M. Tanner ,  Michael C. Leventhal ,  Harold B Noyes

IPC: G06F9/448 ,  G06F8/30

Abstract: A markup language is provided. The markup language describes the composition of automata networks. For example, the markup language uses elements that represent automata processing resources. These resources may include at least one of a state transition element, a counter element, and a Boolean element as respective automata processing resources.

公开(公告)号：US20200327453A1

公开(公告)日：2020-10-15

申请号：US16913582

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Yao Fu ,  Paul Glendenning ,  Tommy Tracy, II ,  Eric Jonas

IPC: G06N20/00 ,  G06N5/00

Abstract: An apparatus includes a processing resource configured to receive a feature vector of a data stream. The feature vector includes a set of feature values. The processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and to receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. The plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. The processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.

公开(公告)号：US10769099B2

公开(公告)日：2020-09-08

申请号：US15534994

申请日：2015-12-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: H04J3/04 ,  G06F15/78 ,  G06N20/00 ,  G06F9/448 ,  G06F1/3225 ,  G06F13/42 ,  G05B19/045 ,  G06F3/06

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

公开(公告)号：US10019311B2

公开(公告)日：2018-07-10

申请号：US15280481

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G11C13/00 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

公开(公告)号：US20180089019A1

公开(公告)日：2018-03-29

申请号：US15280481

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/1076 ,  H03M13/09

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.