公开(公告)号：US20250077103A1

公开(公告)日：2025-03-06

申请号：US18745877

申请日：2024-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06

Abstract: Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.

公开(公告)号：US20250061070A1

公开(公告)日：2025-02-20

申请号：US18790391

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F13/16

Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

公开(公告)号：US20250061056A1

公开(公告)日：2025-02-20

申请号：US18790537

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/02

Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

公开(公告)号：US12217824B2

公开(公告)日：2025-02-04

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Amitava Majumdar ,  Cagdas Dirik ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Danilo Caraccio ,  Niccolo′ Izzo ,  Elliott C. Cooper-Balis ,  Markus H. Geiger

IPC: G11C29/52 ,  G11C7/22 ,  G11C7/24

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US12182413B2

公开(公告)日：2024-12-31

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Yang Lu ,  Edmund Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Danilo Caraccio ,  Robert M. Walker

IPC: G06F11/07 ,  G06F3/06

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

公开(公告)号：US20240428846A1

公开(公告)日：2024-12-26

申请号：US18679393

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C11/4078 ,  G11C11/406

Abstract: Methods, apparatuses, and systems related to detecting and mitigating waterfall attacks are described. A memory device may include a waterfall attack mitigation circuit that is configured to detect, based on the ratio of read commands to write command received by the memory device, whether the memory device is the target of a waterfall attack. Upon detecting that the memory device is the target of a waterfall attack, the waterfall attack mitigation circuit can initiate certain mitigation actions, such as adjusting a threshold used to perform row hammer-related refreshes.

公开(公告)号：US12164803B2

公开(公告)日：2024-12-10

申请号：US17327530

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06 ,  G06F13/16

Abstract: Memory devices and systems with memory-initiated command insertion (and associated methods) are disclosed herein. In one embodiment, a memory device comprises a command insertion terminal configured to be operably connected to a memory controller. The memory device can (i) identify a condition that can be addressed by receiving a command from the memory controller, and (ii) output, via the command insertion terminal, the command or an indication of the condition such that the command is inserted into a command queue of the memory controller. The memory device can include a command terminal over which the memory device can receive the command from the memory controller after the command is inserted in the command queue. In some embodiments, the condition can be a memory region of the memory device requiring a refresh cycle, and the command can be a command to perform a refresh cycle on the memory region.

公开(公告)号：US20240312550A1

公开(公告)日：2024-09-19

申请号：US18598899

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42

Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.

公开(公告)号：US20240312512A1

公开(公告)日：2024-09-19

申请号：US18674284

申请日：2024-05-24

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Randall J. Rooney

IPC: G11C11/4078 ,  G06F13/16 ,  G06F21/55

CPC classification number: G11C11/4078 ,  G06F13/1605 ,  G06F13/1668 ,  G06F21/554 ,  G06F2221/034

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

公开(公告)号：US20240296096A1

公开(公告)日：2024-09-05

申请号：US18588373

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

CPC classification number: G06F11/1096

Abstract: Apparatuses, systems, and methods for selectable expansion of error correction capability. A memory includes an error correction code (ECC) circuit which generates a default number of parity bits based on written data, and uses those parity bits to correct error(s) in the data. A setting of the memory may specify some number of extra bits of parity. When enabled the ECC circuit may generate parity include the default parity and the extra parity. The default parity is stored in an ECC column plane. The extra parity is stored in the data column planes. When the extra parity is enabled, the ECC circuit may detect/correct more bits of error in the data.