公开(公告)号：US11521690B2

公开(公告)日：2022-12-06

申请号：US16488681

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Paolo Papa ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  H03K19/21

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

公开(公告)号：US11341041B2

公开(公告)日：2022-05-24

申请号：US16940015

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F12/02 ,  G06F12/0873

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

公开(公告)号：US20220066926A1

公开(公告)日：2022-03-03

申请号：US17521340

申请日：2021-11-08

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

IPC: G06F12/02 ,  G11C16/10

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

公开(公告)号：US11151052B2

公开(公告)日：2021-10-19

申请号：US16713552

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Laculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US20210240633A1

公开(公告)日：2021-08-05

申请号：US17234062

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US20200226059A1

公开(公告)日：2020-07-16

申请号：US16742215

申请日：2020-01-14

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

IPC: G06F12/02 ,  G11C16/10

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

公开(公告)号：US20200004673A1

公开(公告)日：2020-01-02

申请号：US16024380

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

IPC: G06F12/02 ,  G11C16/10

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.