公开(公告)号：US07964920B2

公开(公告)日：2011-06-21

申请号：US12380497

申请日：2009-02-26

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/11 ,  Y10S257/903

摘要： A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.

公开(公告)号：US07633101B2

公开(公告)日：2009-12-15

申请号：US11484402

申请日：2006-07-11

申请人： Madhukar B. Vora ,  Ashok Kumar Kapoor

发明人： Madhukar B. Vora ,  Ashok Kumar Kapoor

IPC分类号： H01L29/808

CPC分类号： H01L29/808 ,  H01L29/66901

摘要： A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

摘要翻译： 具有自对准金属源，漏极和栅极接触的JFET结构，具有非常低的电阻率和非常小的特征尺寸。 小的源极，漏极和栅极开口被蚀刻在具有根据期望的源极，栅极和漏极开口尺寸设置的厚度的薄介电层中，所述介电层具有氮化物顶层。 金属沉积在所述电介质层的顶部以填充所述开口并且金属被抛光回到电介质层的顶部以实现薄的源极，漏极和栅极接触。 一些实施例包括衬在接触孔上的防漏多晶硅层，并且可能发生尖峰的所有实施例包括阻挡金属层。

公开(公告)号：US20090295427A1

公开(公告)日：2009-12-03

申请号：US12156565

申请日：2008-06-02

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H03K19/173

CPC分类号： H03K19/173 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1778 ,  H01L2924/00

摘要： A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed.

摘要翻译： 开关电路可以包括具有逻辑电路输入和逻辑电路输出的逻辑电路以及耦合以在三个输入/输出（I / O）节点和逻辑电路输入之间提供三个独立路径的至少三个输入晶体管。 开关电路还可以包括耦合到三个I / O节点和逻辑电路输出之间的三个独立路径的至少三个输出晶体管。 还公开了制造这种开关电路和包括这种开关电路的装置和/或系统的方法。

公开(公告)号：US20090282382A1

公开(公告)日：2009-11-12

申请号：US12115991

申请日：2008-05-06

申请人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

发明人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

IPC分类号： G06F17/50 ,  H01L29/80

CPC分类号： H01L23/5283 ,  G06F17/5077 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

摘要翻译： 一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。 电路模型包括一个或多个电路元件的模型。 该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。 另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。 此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子 储存媒介。

公开(公告)号：US20090204935A1

公开(公告)日：2009-08-13

申请号：US12380497

申请日：2009-02-26

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： G06F17/50

CPC分类号： H01L27/11 ,  Y10S257/903

摘要： A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.

公开(公告)号：US20090164963A1

公开(公告)日：2009-06-25

申请号：US11960452

申请日：2007-12-19

申请人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

发明人： Payman Zarkesh-Ha ,  Christopher L. Hamlin ,  Ashok K. Kapoor ,  James S. Koford ,  Madhukar B. Vora

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

摘要翻译： 一种用于对电路进行建模的方法包括：接收网表，其定义多个电路元件之间的多个连接并识别连接的子集。 该方法还包括使用具有第一线宽度的第一组线路路由所识别的连接，并且以第二线宽度路由至少一部分剩余的连接。 第二线宽小于第一线宽度。 该方法还包括用具有第二线宽度的第三组线代替第一组线。

公开(公告)号：US07525163B2

公开(公告)日：2009-04-28

申请号：US11590265

申请日：2006-10-31

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/11

CPC分类号： H01L27/11 ,  Y10S257/903

摘要： A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.

摘要翻译： 半导体器件可以包括通过掺杂半导体衬底形成的至少第一扩散区域和至少通过掺杂通过隔离区域与第一扩散区域分离的半导体衬底形成的第二扩散区域。 至少第一导电线可以包括形成在第一扩散区域和第二扩散区域上并与其接触的半导体材料。 与第一扩散区接触的第一导电线的一部分被掺杂成与第一扩散区相反的导电类型。 包括半导体材料的至少第二导电线与第一导电线平行地形成并且与第一扩散区和第二扩散区相接触并接触。 第二导线的一部分可以与第一扩散区接触并掺杂成与第一扩散区相同的导电类型。 可以将与第二扩散区接触的第二导线的一部分掺杂成与第二扩散区相同的导电类型。

公开(公告)号：US20090039407A1

公开(公告)日：2009-02-12

申请号：US12150079

申请日：2008-04-24

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/105

摘要： A nonvolative memory in the form of a vertical flash EPROM with high density and low cost. A vertical MOS transistor is formed in well etched into a semiconductor substrate, the substrate having source, body and drain regions formed by ion implantation. A thin gate oxide or oxide-nitride-oxide (ONO) layer is formed in the well and a self-aligned floating gate of polysilicon is formed over the gate oxide in the well to overlie the body region. An anisotropic etch is used to form the self aligned floating gate so as to remove all horizontal components and leave no portion of said floating gate extending beyond the perimeter of said well such that its lateral extents are determined by the anisotropic etch and not photolithography. Leff is determined by the energy of the implants used for form the source and drain regions and not by lithography. A deep field oxide bounding parts of said well keeps the coupling ratio good at all feature sizes. A vertically oriented NMOS and PMOS transistor are also disclosed.

摘要翻译： 垂直闪存EPROM形式的非易失性存储器，具有高密度和低成本。 在半导体衬底中形成垂直MOS晶体管，该衬底具有通过离子注入形成的源极，主体和漏极区域。 在阱中形成薄栅氧化物或氧化物 - 氧化物（ONO）层，并且在阱中的栅极氧化物上形成多晶硅的自对准浮置栅极以覆盖在主体区域上。 使用各向异性蚀刻来形成自对准浮动栅极，以便去除所有水平分量，并且不使所述浮栅的任何部分延伸超过所述阱的周边，使得其横向范围由各向异性蚀刻而不是光刻决定。 Leff由用于形成源区和漏区的植入物的能量决定，而不是通过光刻确定。 所述井的深场氧化物界定部分保持所有特征尺寸上的耦合比良好。 还公开了垂直取向的NMOS和PMOS晶体管。

公开(公告)号：US20080099796A1

公开(公告)日：2008-05-01

申请号：US11591916

申请日：2006-11-01

申请人： Madhukar B. Vora

发明人： Madhukar B. Vora

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L27/0623 ,  H01L21/02071 ,  H01L21/28525 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/8249 ,  H01L27/0922 ,  H01L27/098 ,  H01L29/66901 ,  H01L29/78

摘要： A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above a surface of the substrate. The method can also include etching, with a degree of anisotropy, the first layer to form at least a first structure in contact with the first area. Further, in a step separate from the etching step, retention of residual semiconductor material at a junction of the substrate and the at least one electrical isolation structure can be prevented.

摘要翻译： 形成半导体器件的方法可以包括形成与衬底的第一区域接触的第一半导体材料层。 第一区域可以与延伸到衬底中的至少一个电隔离结构相邻，并且具有在衬底的表面上方延伸的顶部部分。 该方法还可以包括具有一定程度的各向异性的蚀刻，第一层以形成与第一区域接触的至少第一结构。 此外，在与蚀刻步骤分离的步骤中，可以防止残留半导体材料在基板和至少一个电隔离结构的接合处的保留。

公开(公告)号：US5668495A

公开(公告)日：1997-09-16

申请号：US639272

申请日：1996-04-23

申请人： Madhukar B. Vora ,  Burnell G. West

发明人： Madhukar B. Vora ,  Burnell G. West

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/173 ,  H03K17/60

CPC分类号： H03K17/6285 ,  H03K17/6257 ,  H03K19/1737

摘要： A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

摘要翻译： 适用于在高速数据通路中使用电流模式逻辑实现现场可编程门阵列的高速开关技术，以及高速数据通路外的CMOS转向逻辑，以实现高速开关逻辑和实现多路复用器，选择器和交叉开关功能 。 还公开了与高速开关逻辑兼容的高速射极跟随器逻辑，用于电平转换，缓冲和提供更多的电流吸收或源极容量。