公开(公告)号：US07492046B2

公开(公告)日：2009-02-17

申请号：US11379582

申请日：2006-04-21

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01L23/48

CPC分类号： H01L23/53276 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N−1 electrically conductive regions to touch the electrically conductive layer.

摘要翻译： 熔丝结构及其操作方法。 熔丝结构操作方法包括提供一种结构。 该结构包括（a）导电层和（b）悬挂在不接触导电层的N个导电区域。 N是正整数，N大于1.N导电区域电连接在一起。 结构操作方法还包括使N个导电区域的第一导电区域与导电层接触而不会使剩余的N-1导电区域接触导电层。

公开(公告)号：US07483285B2

公开(公告)日：2009-01-27

申请号：US12018915

申请日：2008-01-24

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： G11C11/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

摘要： Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

摘要翻译： 存储器件结构。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。

公开(公告)号：US07385839B2

公开(公告)日：2008-06-10

申请号：US11275010

申请日：2005-12-01

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： G11C11/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

摘要： Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

摘要翻译： 结构和操作方法。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。

公开(公告)号：US07102201B2

公开(公告)日：2006-09-05

申请号：US10892467

申请日：2004-07-15

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

摘要翻译： 半导体制造方法和结构，器件和集成电路，其特征在于增强的操作性能。 结构通常包括形成在半导体材料的主体中的第一和第二源极/漏极区域以及限定在第一和第二源极/漏极区域之间的主体中的沟道区域。 在第一和第二源极/漏极区域中的至少一个中设置有多个插塞，每个插塞由容积扩大的材料形成，该压缩应力向沟道区域传递压缩应力。 压缩应变通道区域可能是有用的，例如，用于改善p沟道场效应晶体管（PFET）的操作性能。

公开(公告)号：US20080160312A1

公开(公告)日：2008-07-03

申请号：US12031493

申请日：2008-02-14

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： B32B9/00

CPC分类号： B82Y30/00 ,  B82Y10/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/06 ,  C01B2202/22 ,  C01B2202/34 ,  H01J1/3044 ,  H01J2201/30469 ,  Y10S977/742 ,  Y10S977/84 ,  Y10S977/842 ,  Y10S977/843 ,  Y10T428/30

摘要： Methods for synthesizing carbon nanotubes and structures formed thereby. The method includes forming carbon nanotubes on a plurality of synthesis sites supported by a first substrate, interrupting nanotube synthesis, mounting a free end of each carbon nanotube to a second substrate, and removing the first substrate. Each carbon nanotube is capped by one of the synthesis sites, to which growth reactants have ready access. As the carbon nanotubes lengthen during resumed nanotube synthesis, access to the synthesis sites remains unoccluded.

摘要翻译： 合成碳纳米管的方法及由此形成的结构。 该方法包括在由第一基板支撑的多个合成位置上形成碳纳米管，中断纳米管合成，将每个碳纳米管的自由端安装到第二基板上，以及去除第一基板。 每个碳纳米管被其中一个合成位点封盖，生长反应物可以随时进入。 由于碳纳米管在恢复纳米管合成过程中延长，所以进入合成位点仍未被排除。

公开(公告)号：US20080227264A1

公开(公告)日：2008-09-18

申请号：US11926661

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/76

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US20080206937A1

公开(公告)日：2008-08-28

申请号：US12114180

申请日：2008-05-02

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20080197448A1

公开(公告)日：2008-08-21

申请号：US12112549

申请日：2008-04-30

申请人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US07329567B2

公开(公告)日：2008-02-12

申请号：US11180415

申请日：2005-07-13

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L21/335 ,  H01L21/8232

CPC分类号： H01L27/283 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/70 ,  Y10S977/707 ,  Y10S977/721 ,  Y10S977/724

摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

摘要翻译： 具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。 每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。 每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。 可以在远离通道的口的间隔件的基部中设置间隙。 通过间隙流过催化剂垫的反应物参与纳米管生长。

公开(公告)号：US07211844B2

公开(公告)日：2007-05-01

申请号：US10767039

申请日：2004-01-29

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L29/76

CPC分类号： H01L27/283 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/70 ,  Y10S977/707 ,  Y10S977/721 ,  Y10S977/724

摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

摘要翻译： 具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。 每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。 每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。 可以在远离通道的口的间隔件的基部中设置间隙。 通过间隙流过催化剂垫的反应物参与纳米管生长。