公开(公告)号：US20130093047A1

公开(公告)日：2013-04-18

申请号：US13274122

申请日：2011-10-14

申请人： Jiun-Jie Huang ,  Ling-Sung Wang ,  Chi-Yen Lin

发明人： Jiun-Jie Huang ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/02

CPC分类号： H01L23/5223 ,  H01L23/585 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.

摘要翻译： 金属氧化物 - 金属电容器包括第一电极，第二电极，多个第一指状物和多个第二指状物。 每个第一指状物及其相应的第二指状物平行并由低k电介质材料隔开。 采用保护环包围金属氧化物 - 金属电容器，以防止水分渗透到低k电介质材料中。

公开(公告)号：US20130075725A1

公开(公告)日：2013-03-28

申请号：US13246536

申请日：2011-09-27

申请人： Jiun-Jie Huang ,  Chi-Yen Lin ,  Ling-Sung Wang

发明人： Jiun-Jie Huang ,  Chi-Yen Lin ,  Ling-Sung Wang

IPC分类号： H01L23/52 ,  H01L21/66

CPC分类号： H01L22/34

摘要： A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.

摘要翻译： 半导体晶片具有模具区域和划线区域。 第一虚拟焊盘形成在划线区域的第一测试线区域中，并且填充有作为第一金属层的一部分的第一材料。 在第一金属层上形成第一层间电介质。 第一互连图案形成在管芯区域中并且在第一层间电介质上方，并且第一沟槽图案形成在划线区域的第一测试线区域中以及层间电介质之上。 第一互连图案和第一沟槽图案填充有第二金属层，并且第一沟槽图案在第一虚拟衬垫上方对准。 包括第一沟槽图案和第一虚拟垫的增强的测试线结构在线后端（BEOL）工艺中被形成和探测。

公开(公告)号：US20130049781A1

公开(公告)日：2013-02-28

申请号：US13221594

申请日：2011-08-30

申请人： Jia Yang Ko ,  Ying-Han Chiou ,  Ling-Sung Wang

发明人： Jia Yang Ko ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： G01R31/10 ,  H01L21/768 ,  G06F19/00 ,  H01L23/522

CPC分类号： H01L23/345 ,  G01R31/2875 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure.

摘要翻译： 公开了具有自热结构的半导体器件，其制造方法和测试方法。 在一个实施例中，半导体器件包括工件，设置在工件上方的有源电气结构以及靠近有源电气结构设置的至少一个自热结构。

公开(公告)号：US20130024833A1

公开(公告)日：2013-01-24

申请号：US13618045

申请日：2012-09-14

申请人： Jiun-Jie Huang ,  Chi-Yen Lin ,  Ling-Sung Wang

发明人： Jiun-Jie Huang ,  Chi-Yen Lin ,  Ling-Sung Wang

IPC分类号： G06F17/50

CPC分类号： H01L21/76838 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.

摘要翻译： 一种方法包括从非暂时计算机可读介质检索集成电路的第一布局。 第一布局包括通孔层中的通孔图案，以及在通孔层上方的金属层中的金属线图案。 金属线图案具有到通孔图案的外壳。 外壳增加到第二个外壳以产生集成电路的第二布局。

公开(公告)号：US06916718B2

公开(公告)日：2005-07-12

申请号：US10613606

申请日：2003-07-03

申请人： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

发明人： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

IPC分类号： H01L21/311 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/31116 ,  H01L29/6656

摘要： A method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode is deposited over the layer of gate oxide. The gate electrode is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

摘要翻译： 提供了一种在栅极电极生成期间从栅电极的表面去除衬垫氧化物的方法。 在衬底的表面上形成栅极氧化物层，栅电极层沉积在栅极氧化物层上。 沉积栅电极，在衬垫氧化物上方形成栅极隔离物，暴露衬里氧化物的表面。 所产生的结构被含有N 2 / H 2 O 2的等离子体流渗氮，降低了暴露的衬垫氧化物的蚀刻速率。 然后通过施加湿蚀刻来除去衬里氧化物，对栅电极的接触区域进行浸蚀。

公开(公告)号：US20050059251A1

公开(公告)日：2005-03-17

申请号：US10661793

申请日：2003-09-12

申请人： Chi-An Kao ,  Yung-Chang Chang ,  Yu-Ping Chang ,  Ling-Sung Wang

发明人： Chi-An Kao ,  Yung-Chang Chang ,  Yu-Ping Chang ,  Ling-Sung Wang

IPC分类号： H01L21/311 ,  H01L21/66 ,  H01L21/768 ,  H01L21/44 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L22/20 ,  H01L21/31116 ,  H01L21/76802

摘要： A new method is provided for the creation of a hole through a layer of insulating material. The method provides for combining a feed-forward method with a feed backward method and a high-polymer based hole profile, in order to establish a hole of a constant Critical Dimension for the hole bottom, making the CD of the hole bottom independent of the CD of the opening created through the overlying developed layer of photoresist and independent of the thickness of the layer of insulator material after CMP has been applied to the surface of the insulation layer.

摘要翻译： 提供了一种通过绝缘材料层产生孔的新方法。 该方法提供了前馈方法与进料反向法和高聚合物基孔分布的组合，以便为孔底建立恒定临界尺寸的孔，使得孔底的CD独立于 通过上覆显影层的光致抗蚀剂形成的开口的CD和CMP之后的绝缘体材料层的厚度独立于绝缘层的表面。

公开(公告)号：US06610571B1

公开(公告)日：2003-08-26

申请号：US10068929

申请日：2002-02-07

申请人： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

发明人： Ying-Lin Chen ,  Chiang-Lang Yen ,  Ling-Sung Wang

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/31116 ,  H01L29/6656

摘要： A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

摘要翻译： 提供了一种新的方法，用于在栅电极生成期间从栅电极的表面去除衬垫氧化物。 在衬底的表面上形成栅极氧化物层，在栅极氧化物层上沉积诸如聚酰亚胺的栅电极层。 栅极电极和栅极氧化物层被图案化。 沉积一层衬垫氧化物，在衬垫氧化物上形成栅极间隔物，暴露衬里氧化物的表面。 所产生的结构被含有N 2 / H 2的等离子体流渗氮，降低了暴露的衬垫氧化物的蚀刻速率。 然后通过施加湿蚀刻来除去衬里氧化物，对栅电极的接触区域进行浸蚀。

公开(公告)号：US06242303B1

公开(公告)日：2001-06-05

申请号：US09440138

申请日：1999-11-15

申请人： Ling-Sung Wang ,  Chia-Chen Liu

发明人： Ling-Sung Wang ,  Chia-Chen Liu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for manufacturing an erasable programmable memory is disclosed, and an enlargement of the coupling area between control and floating gates is employed to increase the capacitive-coupling ratio. Firstly, the isolation regions are formed on the substrate. A polysilicon layer is formed on a portion of the control region of the substrate to form an uneven silicon surface. An ion implantation is carried out to form the doped tunnel region and the control gate. A tunnel oxide layer and a non-tunnel oxide layer are formed on the doped tunnel region, and an inter-poly dielectric is formed on the control gate. A floating gate is now deposited on the doped tunnel region and the control gate. Then an inter-layer dielectric is formed and etched to provide the isolation and connect between control gate and interconnects.

摘要翻译： 公开了一种用于制造可擦除可编程存储器的方法，并且采用控制和浮置栅极之间的耦合区域的放大来增加电容耦合比。 首先，在基板上形成隔离区域。 在基板的控制区域的一部分上形成多晶硅层，形成不均匀的硅表面。 进行离子注入以形成掺杂的隧道区域和控制栅极。 在掺杂隧道区域上形成隧道氧化物层和非隧道氧化物层，并且在控制栅极上形成多晶硅电介质。 浮置栅极现在沉积在掺杂的隧道区域和控制栅极上。 然后形成并蚀刻层间电介质以提供控制栅极和互连之间的隔离和连接。

公开(公告)号：US06204127B1

公开(公告)日：2001-03-20

申请号：US09313521

申请日：1999-05-17

申请人： Ling-Sung Wang

发明人： Ling-Sung Wang

IPC分类号： H01L21336

CPC分类号： H01L27/11253

摘要： A method of manufacturing the bit lines of memory. The method includes the steps of forming a mask over a substrate, and then patterning the mask layer to form an opening that exposes a portion of the substrate. Thereafter, a portion of the exposed substrate is removed to form a trench in the substrate. Next, the mask layer is removed. Finally, conductive material is deposited into the trench to form a bit line.

摘要翻译： 一种制造存储器位线的方法。 该方法包括以下步骤：在衬底上形成掩模，然后对掩模层进行构图以形成露出衬底的一部分的开口。 此后，去除暴露的衬底的一部分以在衬底中形成沟槽。 接下来，去除掩模层。 最后，将导电材料沉积到沟槽中以形成位线。

公开(公告)号：US6143606A

公开(公告)日：2000-11-07

申请号：US61618

申请日：1998-04-16

申请人： Ling-Sung Wang ,  Ko-Hsing Chang

发明人： Ling-Sung Wang ,  Ko-Hsing Chang

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In this method for manufacturing a split-gate flash memory cell, a floating gate and a control gate are formed over a substrate, and then first spacers are formed on the sidewalls of the gate structure. Next, a polysilicon layer is deposited over the gate structure and the substrate, and second spacers are formed on the sidewalls of the polysilicon layer. A self-aligned ion implantation process is performed, using the second spacers as a mask, implanting ions into the semiconductor substrate to form a drain region. This maintains the channel length. After removing the second spacers, another ion implantation process is performed to create a source region in the semiconductor substrate. During the second implantation, the polysilicon layer offers some protection for the semiconductor substrate, maintaining the capacity for tunneling. Finally, a conductive layer is formed over the polysilicon layer, and the conductive layer combined with the polysilicon layer forms the select gate.

摘要翻译： 在用于制造分离栅极闪存单元的方法中，在衬底上形成浮栅和控制栅极，然后在栅极结构的侧壁上形成第一间隔物。 接下来，在栅极结构和衬底上沉积多晶硅层，并且在多晶硅层的侧壁上形成第二间隔物。 执行自对准离子注入工艺，使用第二间隔物作为掩模，将离子注入到半导体衬底中以形成漏极区。 这保持通道长度。 在去除第二间隔物之后，执行另一离子注入工艺以在半导体衬底中产生源区。 在第二次注入期间，多晶硅层为半导体衬底提供了一些保护，保持了隧道的容量。 最后，在多晶硅层上形成导电层，与多晶硅层结合的导电层形成选择栅极。