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公开(公告)号：US20210409137A1
公开(公告)日：2021-12-30
申请号：US16910193
申请日：2020-06-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron Mula , Dotan David Levi , Ran Ravid , Guy Lederman
Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.
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公开(公告)号：US20210392065A1
公开(公告)日：2021-12-16
申请号：US16900931
申请日：2020-06-14
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Sela , Liron Mula , Ran Ravid , Guy Lederman , Dotan David Levi
Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.
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公开(公告)号：US10594617B2
公开(公告)日：2020-03-17
申请号：US16132423
申请日：2018-09-16
Applicant: Mellanox Technologies, Ltd.
Inventor： Alex Shpiner , Sagi Kuks , Liron Mula , Gil Levy
IPC: H04L12/805 , H04L12/833 , H04L12/863 , H04L12/935 , H04L12/823 , G06F17/18
Abstract: A network device includes circuitry and multiple ports. The circuitry is configured to hold a definition of a normalization function that determines, based on (i) a reference probability of applying a congestion indication operation to packets having a predefined reference packet-size and (ii) a packet-size parameter, a normalized probability of applying the congestion indication operation to packets whose size equals the packet-size parameter. The normalization function depends exponentially on a ratio between the packet-size parameter and the reference packet-size. The circuitry id configured to store packets in a queue, and to schedule transmission of at least some of the queued packets via an output port, to calculate the normalized probability for a given packet, by applying the normalization function to an actual reference probability and an actual size of the given packet, and randomly apply a congestion indication operation to the given packet, in accordance with the normalized probability.
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公开(公告)号：US20190089644A1
公开(公告)日：2019-03-21
申请号：US16132423
申请日：2018-09-16
Applicant: Mellanox Technologies, Ltd.
Inventor： Alex Shpiner , Sagi Kuks , Liron Mula , Gil Levy
IPC: H04L12/805 , H04L12/833 , H04L12/823 , H04L12/863 , H04L12/935
Abstract: A network device includes circuitry and multiple ports. The circuitry is configured to hold a definition of a normalization function that determines, based on (i) a reference probability of applying a congestion indication operation to packets having a predefined reference packet-size and (ii) a packet-size parameter, a normalized probability of applying the congestion indication operation to packets whose size equals the packet-size parameter. The normalization function depends exponentially on a ratio between the packet-size parameter and the reference packet-size. The circuitry id configured to store packets in a queue, and to schedule transmission of at least some of the queued packets via an output port, to calculate the normalized probability for a given packet, by applying the normalization function to an actual reference probability and an actual size of the given packet, and randomly apply a congestion indication operation to the given packet, in accordance with the normalized probability.
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公开(公告)号：US12231343B2
公开(公告)日：2025-02-18
申请号：US17902936
申请日：2022-09-05
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron Mula , Lion Levi , Yuval Shpigelman
IPC: H04L47/26 , H04L47/10 , H04L47/2425 , H04L47/30 , H04L47/62
Abstract: A network element includes a transmit-queue for transmitting packets from at least two sources, each source having a predefined priority level, to a headroom buffer in a peer network element. Flow-control circuitry receives from the peer network element signaling that indicates a number of credits for transmitting packets to the peer network element, manages a current number of credits available for transmission from the transmit-queue, responsive to the signaling, selects a threshold priority based on the current number of credits for the transmit-queue; and transmits packets associated with data sources of the transmit-queue that are higher in priority than the threshold priority, and refrain from transmitting other packets associated with the transmit-queue.
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Patent Agency Ranking
公开(公告)号：US20250039109A1
公开(公告)日：2025-01-30
申请号：US18225562
申请日：2023-07-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Eran Gil Beracha , Liron Mula , Barak Gafni , Gil Levy , Aviv Kfir
IPC: H04L49/9047 , H04L47/125 , H04L47/62
Abstract: A system, a computing system, and a switch are provided. In one example, a system for routing data to one of a plurality of queues comprises a processor to poll a depth of one or more queues of the plurality of queues, determine a weight for each polled queue based on the depth of each polled queue, and route data received via a port to a first queue of the plurality of queues based on the determined weight for each polled queue.
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公开(公告)号：US20250038871A1
公开(公告)日：2025-01-30
申请号：US18914324
申请日：2024-10-14
Applicant: Mellanox Technologies, Ltd.
Inventor： Liron Mula , Elad Mentovich , Paraskevas Bakopoulos , Eitan Zahavi , Sagi Kuks
Abstract: A system includes multiple processors to communicate with one another at predefined time slots. A given processor among the processors is to (i) hold a predetermined schedule plan that specifies which of the other processors in the system are accessible to the given processor at which of the time slots, the predetermined schedule plan having been determined before receiving data for transmission from the given processors to the other processors, (ii) queue data that is destined to one or more of the other processors, and (iii) transmit the queued data in accordance with the predetermined schedule plan.
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公开(公告)号：US20240373379A1
公开(公告)日：2024-11-07
申请号：US18225525
申请日：2023-07-24
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Wojciech Wasko , Liron Mula , Ariel Almog , Bar Shapira , Guy Lederman
IPC: H04W56/00
Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.
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公开(公告)号：US20240373378A1
公开(公告)日：2024-11-07
申请号：US18143509
申请日：2023-05-04
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Wojciech Wasko , Ran Ravid , Guy Lederman , Liron Mula , Eitan Zahavi , Peter Paneah
IPC: H04W56/00
Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.
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60.发明授权公开(公告)号：US12120035B2
公开(公告)日：2024-10-15
申请号：US17844362
申请日：2022-06-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron Mula , Aviv Kfir , Miri Shtaif , Eran Gil Beracha
IPC: H04L47/56 , H04L43/0852 , H04L47/625
CPC classification number: H04L47/56 , H04L43/0852 , H04L47/625
Abstract: A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.
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