公开(公告)号：US08619455B2

公开(公告)日：2013-12-31

申请号：US13230735

申请日：2011-09-12

申请人： Tadashi Miyakawa ,  Daisaburo Takashima

发明人： Tadashi Miyakawa ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and then set the second bitline to a second power-supply voltage different from the first power-supply voltage; a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.

摘要翻译： 一个实施例提供一种铁电存储器，包括：各自包括铁电存储器的存储单元; 配置为从存储器单元读出单元信号的第一和第二位线; 第一电路，被配置为当所述单元信号从所述存储单元读取到所述第一位线时，将所述第二位线的电压修改为第一电源电压，然后将所述第二位线设置为不同的第二电源电压 从第一个电源电压; 第二电路，被配置为在所述第一电路将所述第二位线设置为所述第二电源电压之后，将所述第二位线设置为参考电压; 以及第三电路，被配置为放大读取单元信号的第一位线与设定参考电压的第二位线之间的电压差。

公开(公告)号：US08331191B2

公开(公告)日：2012-12-11

申请号：US13233694

申请日：2011-09-15

申请人： Takeshi Hioka ,  Daisaburo Takashima

发明人： Takeshi Hioka ,  Daisaburo Takashima

IPC分类号： G11C8/00

CPC分类号： G11C16/32 ,  G11C16/30

摘要： According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.

摘要翻译： 根据一个实施例，半导体集成电路器件包括输出电路，该输出电路包括具有第一晶体管的反相器和电流路径串联连接在第一电源电压和第二电源电压之间的第二晶体管，第一二极管电路 其一端连接到第一电源电压，另一端连接到第一晶体管的控制端，以及调节电路，形成用于对第一晶体管的控制端的电荷进行放电的电流通路 当输入时钟处于第一电平时，晶体管到第二电源电压。

公开(公告)号：US08248835B2

公开(公告)日：2012-08-21

申请号：US12718800

申请日：2010-03-05

申请人： Tadashi Miyakawa ,  Daisaburo Takashima

发明人： Tadashi Miyakawa ,  Daisaburo Takashima

IPC分类号： G11C11/12

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

摘要： Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit.

摘要翻译： 半导体存储器包括具有铁电电容器和单元晶体管的存储单元，连接到存储单元的位线，连接到单元晶体管的栅电极的字线，连接到铁电电容器的两个电极之一的板线，连接在每对位线之间的读出放大器 。 此外，为了对每个位线施加外部电压，提供了测试焊盘，分别对应于位线提供了测试晶体管，每个测试晶体管连接在测试焊盘和每个位线之间，疲劳测试偏置 电路连接到位于测试焊盘和测试晶体管之间的第一节点。 测试晶体管在第一测试中被共享，以通过测试焊盘从外部施加第一电压到铁电电容器，以及从疲劳测试偏置电​​路向铁电电容器施加第二电压的第二测试。

公开(公告)号：US08174913B2

公开(公告)日：2012-05-08

申请号：US12703548

申请日：2010-02-10

申请人： Daisuke Hashimoto ,  Daisaburo Takashima

发明人： Daisuke Hashimoto ,  Daisaburo Takashima

IPC分类号： G11C7/00 ,  G11C17/18 ,  G11C11/22 ,  G11C11/34 ,  G11C8/00

CPC分类号： G11C29/24 ,  G11C11/22 ,  G11C17/143 ,  G11C29/785

摘要： A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.

摘要翻译： 存储器包括单元区域; 包括备用区的备用区; 熔丝区域，其存储访问所述备用块而不是补救目标块所需的补救信息，所述熔丝区域包括所述补救目标块中的无缺陷单元，或者包括所述备用区域的第一块中的单元; 存储用于识别补救目标块的块地址的初始读取熔丝或分配为熔丝区的第一块的初始读取熔丝，以及用于选择补救目标块中的区域或分配为熔丝区域的第一块中的区域的选择地址; 以及控制器，被配置为基于所述块地址和所述选择地址从所述保险丝区域获取补救信息，并且基于所述补救信息来将对所述补救目标块的访问改变为对所述备用块的访问。

公开(公告)号：US08134855B2

公开(公告)日：2012-03-13

申请号：US12404157

申请日：2009-03-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C29/50016

摘要： A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage.

摘要翻译： 在测试模式下，驱动电路和预充电电路将固定电位施加到位线，同时对板线施加第二板线电压。 然后，将位线从第一位线预充电电位切换到浮置状态，并且将板线电压从第二板线电压升高到板线电压。

公开(公告)号：US20120060066A1

公开(公告)日：2012-03-08

申请号：US13297327

申请日：2011-11-16

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： G06F11/16

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US07990750B2

公开(公告)日：2011-08-02

申请号：US12563924

申请日：2009-09-21

申请人： Hidehiro Shiga ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.

摘要翻译： 本发明实施例的铁电存储器包括布置在第一互连层（m为正整数）中的m条线，布置在第二互连层（n为正整数）中的n条位线，m×n个存储器单元布置 在m个平面阵列和n个位线的m×n个交点处，m×n个存储单元中的每一个包括串联连接在n个位线中的任何一个之间的铁电电容器和齐纳二极管。

公开(公告)号：US07965536B2

公开(公告)日：2011-06-21

申请号：US12560206

申请日：2009-09-15

申请人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

发明人： Daisuke Hashimoto ,  Daisaburo Takashima ,  Hidehiro Shiga

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.

摘要翻译： 根据本发明的一个方面，提供了一种铁电存储器件，它包括：一个单元单元，包括：具有第一源极，第一漏极和第一栅极的第一选择晶体管，第一源极和第一漏极之一 连接到位线; 以及具有多个第一存储单元的存储单元单元，每个第一存储单元包括第一铁电电容器和第一存储晶体管; 以及铁电存储器熔丝，包括：第二选择晶体管，具有连接到第二选择线的第二源极，第二漏极和第二栅极，所述第二源极和所述第二漏极中的一个连接到所述位线的一端; 以及具有多个第二存储单元的存储器熔丝单元，每个第二存储单元包括第二铁电电容器和第二存储晶体管。

公开(公告)号：US20110058428A1

公开(公告)日：2011-03-10

申请号：US12877862

申请日：2010-09-08

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/34

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected to a first signal line, a source of a first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of a second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of a third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.

摘要翻译： 根据一个实施例，第一节点连接到第二PMOS的栅极和第二NMOS的栅极，第二节点连接到第一PMOS的栅极和第一NMOS的栅极，第一NMOS的栅极 晶体管连接到第一信号线，第一晶体管的源极连接到第一节点，第一晶体管的漏极连接到第二节点，第二晶体管的栅极连接到第二节点， 第二晶体管的源极连接到第三节点，第二晶体管的漏极连接到第二信号线，第三晶体管的栅极连接到第三信号线，第三晶体管的源极连接 到第四信号线，并且第三晶体管的漏极连接到第三节点。

公开(公告)号：US07902913B2

公开(公告)日：2011-03-08

申请号：US12618373

申请日：2009-11-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.

摘要翻译： 根据本发明的一个方面，提供了一种参考电压产生电路，包括：具有第一栅极，第一源极和第一漏极的第一晶体管; 第二晶体管，具有连接到第一栅极的第二栅极，连接到第一源极和第二漏极的第二源极; 连接在地和V节点之间的第一二极管; 连接在V节点和第一漏极之间的第一电阻器; 连接在地和V +节点之间的第二二极管和第二电阻器; 连接在V +节点和第一漏极之间的第三电阻器; 运算放大器，包括连接到V +节点和V节点的输入端口以及连接到第一门极和第二门极的输出端口; 以及连接在地和第二漏极之间的第四电阻器。