公开(公告)号：US11545428B2

公开(公告)日：2023-01-03

申请号：US16999358

申请日：2020-08-21

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

公开(公告)号：US20210043560A1

公开(公告)日：2021-02-11

申请号：US16741921

申请日：2020-01-14

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.

公开(公告)号：US20210020568A1

公开(公告)日：2021-01-21

申请号：US16549635

申请日：2019-08-23

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L21/768

Abstract: In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.

公开(公告)号：US10658453B2

公开(公告)日：2020-05-19

申请号：US16037889

申请日：2018-07-17

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Yaojian Leng ,  Greg Stom

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/02

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.

公开(公告)号：US09679844B2

公开(公告)日：2017-06-13

申请号：US15184748

申请日：2016-06-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Hiroki Sato

IPC: H01L21/321 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01C7/006 ,  H01C17/075 ,  H01C17/288 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53228 ,  H01L28/24

Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.

公开(公告)号：US20160372420A1

公开(公告)日：2016-12-22

申请号：US15184748

申请日：2016-06-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Hikori Sato

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01C7/006 ,  H01C17/075 ,  H01C17/288 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53228 ,  H01L28/24

Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.

Abstract translation: 在本公开的一些实施例中，在铜工艺模块上完成铜化学机械抛光（CMP）工艺之后制造薄膜电阻器的方法可以包括：跨越至少两个结构沉积电介质阻挡层; 在所述电介质阻挡层顶部沉积作为硬掩模的第二介电层; 使用光刻法构图沟槽; 通过硬掩模蚀刻沟槽并停留在介质屏障中或介质屏障上; 从光刻工艺中除去任何剩余的光致抗蚀剂; 通过所述电介质阻挡层蚀刻所述沟槽，从而暴露所述至少两个铜结构中的每一个的铜表面; 以及将薄膜电阻器材料沉积到所述沟槽中并桥接跨越所形成的至少两个暴露的铜表面。

公开(公告)号：US20240170390A1

公开(公告)日：2024-05-23

申请号：US18104372

申请日：2023-02-01

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L28/75 ,  H01L28/91

Abstract: A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

公开(公告)号：US20240088201A1

公开(公告)日：2024-03-14

申请号：US17988285

申请日：2022-11-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

CPC classification number: H01L28/24 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0629

Abstract: An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.

公开(公告)号：US20230420495A1

公开(公告)日：2023-12-28

申请号：US17874482

申请日：2022-07-27

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223

Abstract: A multi-capacitor module includes a nested metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, and a third electrode formed over the cup-shaped second insulator. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor physically nested in the first capacitor.

公开(公告)号：US11804803B2

公开(公告)日：2023-10-31

申请号：US16837660

申请日：2020-04-01

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H03B5/12 ,  H01F27/28 ,  H01L21/70 ,  H01L27/01 ,  H01L49/02

CPC classification number: H03B5/12 ,  H01F27/2804 ,  H01L21/707 ,  H01L27/016 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809

Abstract: A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.