公开(公告)号：US11200179B2

公开(公告)日：2021-12-14

申请号：US16801949

申请日：2020-02-26

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna ,  Nadav Grosz

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F1/24 ,  G06F21/79 ,  G06F12/06 ,  G06F12/02

Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

公开(公告)号：US11182102B2

公开(公告)日：2021-11-23

申请号：US16235168

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US10970228B2

公开(公告)日：2021-04-06

申请号：US16220608

申请日：2018-12-14

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna ,  Nadav Grosz

IPC: G06F3/00 ,  G06F12/1009 ,  H03M7/46 ,  G06F3/06 ,  G06F5/06

Abstract: Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and storing the encoded physical address as a map entry of a logical-to-physical (L2P)) table in a cache random access memory of the memory controller.

公开(公告)号：US20210064526A1

公开(公告)日：2021-03-04

申请号：US16552246

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz

IPC: G06F12/08 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for remapping data of flash memory indexed by logical block addresses (LBAs) of a host device in response to re-map requests received at a flash memory system from the host device or in response to re-map requests generated at the flash memory system.

公开(公告)号：US20210056021A1

公开(公告)日：2021-02-25

申请号：US16548107

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F12/0804 ,  G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: Devices and techniques for logical-to-physical (L2P) map (e.g., table) synchronization in a managed memory device are described herein. For example, a plaintext portion of an L2P map may be updated in a managed memory device. In response to updating the plaintext portion of the L2P map, the updated portion can be obfuscated to create an obfuscated version of the updated portion of the L2P map. Both the updated portion and the obfuscated version of the updated portion can be saved in storage of the memory device. When a request from a host for the updated portion of the L2P map is received, the memory device can provide the obfuscated version of the portion from the storage.

公开(公告)号：US10795746B2

公开(公告)日：2020-10-06

申请号：US16219292

申请日：2018-12-13

Applicant: Micron Technology, Inc.

Inventor： Jonathan Parry ,  Nadav Grosz

IPC: G06F11/07 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237

Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

公开(公告)号：US10782345B2

公开(公告)日：2020-09-22

申请号：US16022039

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F11/00 ,  G01R31/317 ,  G01R31/3177 ,  G06F11/263

Abstract: Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die.

公开(公告)号：US20240329721A1

公开(公告)日：2024-10-03

申请号：US18597462

申请日：2024-03-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US12008257B2

公开(公告)日：2024-06-11

申请号：US17994543

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F3/06 ,  H04L9/32

CPC classification number: G06F3/0652 ,  G06F3/0623 ,  G06F3/0679 ,  H04L9/32

Abstract: A memory device includes a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to encrypt write data received via the communication interface to produce encrypted data, program a portion of the memory cells of the memory array with the encrypted data, read the encrypted data from the portion of the memory cells in response to a memory read request, decrypt the read encrypted data to produce read decrypted data only for portions of the read encrypted data not stored in purged regions of the memory array.

公开(公告)号：US20230376205A1

公开(公告)日：2023-11-23

申请号：US17663722

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Marco Onorato ,  Luca Porzio ,  Roberto Izzi ,  Nadav Grosz

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.