公开(公告)号：US20230019910A1

公开(公告)日：2023-01-19

申请号：US17954023

申请日：2022-09-27

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Alex Tang

IPC: G06F3/06

Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

公开(公告)号：US11481119B2

公开(公告)日：2022-10-25

申请号：US16874389

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Ying Yu Tai ,  Ning Chen ,  Jiangli Zhu ,  Alex Tang

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

公开(公告)号：US11461030B2

公开(公告)日：2022-10-04

申请号：US16916926

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Yueh-Hung Chen ,  Chih-Kuo Kao ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G06F1/04

Abstract: Methods, systems, and devices for one or more clock domain crossing queues are described. A queue can receive, from a first clock domain, a first command to store data in the queue. The queue can store the data at a first location indicated by a first pointer. The queue can receive, from the first clock domain, a second command to cause the second clock domain to retrieve the data from the queue. The queue can generate, based on receiving the second command, a third command synchronized with a clock of the second clock domain and to cause the second clock domain to retrieve the data. The queue can retrieve the data from the first location in the queue indicated by a second pointer associated with retrieving data based at least in part on generating the third command. The queue can transmit, to the second clock domain, the data.

公开(公告)号：US11281533B2

公开(公告)日：2022-03-22

申请号：US16947311

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu ,  Zhengang Chen

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/37

Abstract: Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.

公开(公告)号：US20220035572A1

公开(公告)日：2022-02-03

申请号：US17506246

申请日：2021-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A processing device, operatively coupled with a memory device, performs operations including receiving a write request from a host system at a first time, the write request identifying first data to be stored in a segment of the memory device, determining whether a pre-read voltage level of the write request satisfies a pre-read voltage level criterion pertaining to a write-to-write time interval for the segment, wherein the write-to-write time interval is defined by the first time and a second time corresponding to a last time at which the segment was written, and responsive to determining that the pre-read voltage level satisfies the pre-read voltage level criterion pertaining to the write-to-write time interval, performing a pre-read operation on the segment using the pre-read voltage level to determine second data currently stored in the segment.

公开(公告)号：US20210365391A1

公开(公告)日：2021-11-25

申请号：US17392192

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F13/16 ,  G06F13/42 ,  G06F11/07

Abstract: An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

公开(公告)号：US20210286665A1

公开(公告)日：2021-09-16

申请号：US17335433

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F11/07 ,  G06F13/12 ,  G06F13/16

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

公开(公告)号：US20210089476A1

公开(公告)日：2021-03-25

申请号：US17112748

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Samir Mittal

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.

公开(公告)号：US10942809B2

公开(公告)日：2021-03-09

申请号：US16228632

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: Data to be stored at a memory sub-system can be received. A usage characteristic of the memory sub-system can be determined. The received data can be encoded to generate a codeword with a number of parity bits. A portion of the number of parity bits of the generated codeword can be removed based on the usage characteristic of the memory sub-system. Furthermore, the codeword can be stored without the removed portion of the number of parity bits.

公开(公告)号：US20210064248A1

公开(公告)日：2021-03-04

申请号：US16555997

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.