公开(公告)号：US11288214B2

公开(公告)日：2022-03-29

申请号：US17093104

申请日：2020-11-09

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06 ,  G06F12/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US11157412B2

公开(公告)日：2021-10-26

申请号：US16694172

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Dhawal Bavishi

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/02 ,  G11C11/408 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16

Abstract: Various embodiments described herein provide for selectively sending a read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system based on a predicted row status of a given memory device (e.g., random access memory (RAM)-based cache) of the memory sub-system.

公开(公告)号：US20200379667A1

公开(公告)日：2020-12-03

申请号：US16995122

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US10831682B2

公开(公告)日：2020-11-10

申请号：US16103585

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06 ,  G06F12/06

Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

公开(公告)号：US20200065027A1

公开(公告)日：2020-02-27

申请号：US16111974

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US10387121B2

公开(公告)日：2019-08-20

申请号：US16213835

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jesse F. Lovitt ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F7/58 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

公开(公告)号：US20190108000A1

公开(公告)日：2019-04-11

申请号：US16213835

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jesse F. Lovitt ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F7/58 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G06F7/588 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

公开(公告)号：US20180275964A1

公开(公告)日：2018-09-27

申请号：US15995748

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jesse F. Lovitt ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F7/58 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G06F7/588 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device to perform sensing a first voltage on a first sense line coupled to the sense amplifier and sensing a second voltage on a complementary second sense line coupled to the sense amplifier. The example method further includes generating a random number by detecting a voltage differential between the first sense line and the complementary second sense line.

公开(公告)号：US09921777B2

公开(公告)日：2018-03-20

申请号：US15184516

申请日：2016-06-16

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  James J. Shawver

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/4097

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

公开(公告)号：US20170358331A1

公开(公告)日：2017-12-14

申请号：US15687813

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C7/1006

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.