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54 条记录 (耗时 0.026 秒)

    Display apparatus and display-apparatus driving method
    51.
    发明申请
    Display apparatus and display-apparatus driving method 失效
    显示装置和显示装置驱动方法

    公开(公告)号：US20090273617A1

    公开(公告)日：2009-11-05

    申请号：US12385689

    申请日：2009-04-16

    申请人： Takao Tanikame ,  Seiichiro Jinta

    发明人： Takao Tanikame ,  Seiichiro Jinta

    IPC分类号： G09G5/10 ,  G09G3/32

    CPC分类号： G09G3/3233 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0262

    摘要： Disclosed herein is a driving method for driving a, display apparatus, the display apparatus including: N×M light emitting units; M scan lines; N data lines; a driving circuit provided for each of the light emitting units to serve as a circuit having a signal writing transistor, a device driving transistor, a capacitor and a first switch circuit; and a light emitting device.

    摘要翻译： 这里公开了一种用于驱动显示装置的驱动方法，该显示装置包括：NxM个发光单元; M扫描线; N条数据线 为每个发光单元设置用作具有信号写入晶体管的电路的驱动电路，器件驱动晶体管，电容器和第一开关电路; 和发光装置。

    Semiconductor device, display panel and electronic equipment
    53.
    发明申请
    Semiconductor device, display panel and electronic equipment 有权
    半导体器件，显示面板和电子设备

    公开(公告)号：US20090237123A1

    公开(公告)日：2009-09-24

    申请号：US12320962

    申请日：2009-02-10

    申请人： Seiichiro Jinta

    发明人： Seiichiro Jinta

    IPC分类号： H03B1/00

    CPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/043 ,  G11C19/184

    摘要： The present invention provides a semiconductor device having a buffer circuit formed on an insulating substrate using single-channel type thin film transistors, wherein the buffer circuit has an output stage which including first and second thin film transistors connected in series between first and second power sources, and the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor.

    摘要翻译： 本发明提供了一种半导体器件，其具有使用单沟道型薄膜晶体管形成在绝缘衬底上的缓冲电路，其中缓冲电路具有输出级，该输出级包括串联连接在第一和第二电源之间的第一和第二薄膜晶体管 ，并且输出级的输出端电位以适合于控制第一薄膜晶体管的设定信号的输入定时以及适于控制第一薄膜晶体管的复位信号以互补的方式切换到第一或第二电源的电位 第二薄膜晶体管。

    Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus
    54.
    发明申请
    Level conversion circuit, power supply voltage generation circuit, shift circuit, shift register circuit, and display apparatus 有权
    电平转换电路，电源电压产生电路，移位电路，移位寄存器电路和显示装置

    公开(公告)号：US20060061385A1

    公开(公告)日：2006-03-23

    申请号：US11195837

    申请日：2005-08-03

    申请人： Seiichiro Jinta ,  Ryuya Koike

    发明人： Seiichiro Jinta ,  Ryuya Koike

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018521 ,  G09G3/32 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/18 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

    摘要： The present invention provides a level conversion circuit including first and second transistors, a clock terminal, first switch means, second switch means, and a capacitance element. The first and second transistors are of the opposite conduction types to each other connected in series between a first power supply potential and a second power supply potential. The clock terminal is inputted a clock signal. The first switch means is connected between the clock terminal and the gate of the first transistor and has an on state when a circuit operation control signal is in an active state. The second switch means is connected between the second power supply potential and the gate of the second transistor and has an off state when the circuit operation control signal is in an active state. The capacitance element is connected between the clock terminal and the gate of the second transistor.

    摘要翻译： 本发明提供了包括第一和第二晶体管，时钟端子，第一开关装置，第二开关装置和电容元件的电平转换电路。 第一和第二晶体管彼此相反的导电类型彼此串联连接在第一电源电位和第二电源电位之间。 时钟端子输入时钟信号。 第一开关装置连接在时钟端子和第一晶体管的栅极之间，并且当电路操作控制信号处于活动状态时具有导通状态。 第二开关装置连接在第二电源电位和第二晶体管的栅极之间，并且当电路操作控制信号处于活动状态时具有断开状态。 电容元件连接在时钟端子和第二晶体管的栅极之间。