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公开(公告)号：US20190163220A1
公开(公告)日：2019-05-30
申请号：US16191355
申请日：2018-11-14
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
Abstract: A power supply device includes an input terminal, a regulated voltage output terminal, a switch, a first transistor, and a current split circuit. The input terminal receives a first control voltage. The regulated voltage output terminal outputs an output voltage. The switch has a first terminal coupled to the input terminal, a second terminal, and a control terminal. The first transistor has a first terminal coupled to a voltage terminal, a second terminal coupled to the regulated voltage output terminal, and a control terminal coupled to the second terminal of the switch. The current split circuit is coupled to the voltage terminal and the regulated voltage output terminal. The current split circuit receives the first control voltage or a second control voltage, and includes a second transistor coupled between the voltage terminal and the regulated voltage output terminal.
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Patent Agency Ranking
公开(公告)号：US20190123747A1
公开(公告)日：2019-04-25
申请号：US16111238
申请日：2018-08-24
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
IPC: H03K19/003
CPC classification number: H03K19/00315 , H03K19/0013 , H03K19/0016 , H03K19/003 , H03K19/017 , H03K19/01707 , H03K19/20
Abstract: An inverter includes a first system voltage terminal, a second system voltage terminal, an output terminal, a plurality of P-type transistors, a plurality of N-type transistors, and a voltage drop impedance element. The first system voltage terminal receives a first voltage, and the second system voltage terminal receives a second voltage. The plurality of P-type transistors are coupled in series between the first system voltage terminal and the output terminal. The plurality of N-type transistors are coupled in series between the output terminal and the second system voltage terminal. The voltage drop impedance element is coupled in parallel with a first N-type transistor of the plurality of N-type transistors, and the impedance of the voltage drop impedance element is smaller than the impedance of the first N-type transistor when the first N-type transistor is turned off.
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公开(公告)号：US10256808B2
公开(公告)日：2019-04-09
申请号：US15825116
申请日：2017-11-29
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
Abstract: A bandgap reference circuit includes a voltage generation circuit, a capacitor and a clamping control circuit. The voltage generation circuit is used to generate a current on an operation terminal. The capacitor includes a first terminal coupled to the operation terminal, and a second terminal coupled to a first reference voltage terminal. The clamping control circuit is coupled between the operation terminal and a second reference voltage terminal. The clamping control circuit includes a switch and a clamping unit, and is used to allow part of the current flowing through the clamping unit to the second reference voltage terminal when the switch is turned on.
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公开(公告)号：US10248149B2
公开(公告)日：2019-04-02
申请号：US15839189
申请日：2017-12-12
Applicant: RICHWAVE TECHNOLOGY CORP.
Inventor： Chih-Sheng Chen , Tien-Yun Peng , Jhao-Yi Lin
Abstract: A bias circuit includes a first transistor, a second transistor, a first resistor and a second resistor. The first end of the first transistor is coupled to a first voltage source. One end of the first resistor is coupled to the second end of the first transistor, and the other end of the first resistor is coupled to the control terminal of the first transistor. The first end of the second transistor is coupled to a second voltage source, and the second end of the second transistor is coupled to the control terminal of the first transistor. One end of the second resistor is coupled to the other end of the first resistor, and the other end of the second resistor is coupled to the control terminal of the second transistor.
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公开(公告)号：US20190068195A1
公开(公告)日：2019-02-28
申请号：US16102685
申请日：2018-08-13
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
IPC: H03K19/094 , H02H9/02 , H03K19/0175 , H03K19/173 , H03H17/02
Abstract: A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.
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公开(公告)号：US20170117808A1
公开(公告)日：2017-04-27
申请号：US15398726
申请日：2017-01-05
Applicant: RichWave Technology Corp.
Inventor： Chih-Sheng Chen , Tien-Yun Peng
CPC classification number: H02M3/24 , H02M1/36 , H02M3/07 , H02M7/103 , H02M2003/075
Abstract: A voltage generator including an oscillator having an output, a charge pump having an input and an output, the input of the charge pump being coupled to the output of the oscillator, a smoothing capacitor, a resistor having an input end and an output end, wherein the input end is coupled to the charge pump and the output end is coupled to the smoothing capacitor, and a shorting element connected in parallel with the resistor and which, when turned on, causes the resistor to be at least partially bypassed, wherein the voltage generator is configured to supply voltage to a radio frequency (RF) switch via the smoothing capacitor, and a frequency of the oscillator is controlled to be faster during a switching period of the RF switch.
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