公开(公告)号：US6000014A

公开(公告)日：1999-12-07

申请号：US834490

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08

CPC分类号： G06F12/0864

摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes is then defined using a mapping function which operates on the encoded addresses, such that the program instructions may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The program instructions can modify the original addresses by setting a plurality of programmable fields. Application software may provide the program instructions, wherein congruence classes are programmed based on a particular procedure of the application software which is running on the processor, that might otherwise run with excessive "striding" of the cache. Alternatively, operating-system software may monitor allocation of memory blocks in the cache and provides the program instructions to modify the original addresses based on the allocation of the memory blocks, to lessen striding.

摘要翻译： 公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。 程序指令被加载到处理器中，用于修改存储器件中的存储器块的原始地址以产生编码的地址。 然后使用对编码地址进行操作的映射函数来定义多个高速缓存一致等级，使得程序指令可以用于任意地将给定的一个原始地址分配给高速缓存一致性类的特定一个。 程序指令可以通过设置多个可编程字段来修改原始地址。 应用软件可以提供程序指令，其中根据在处理器上运行的应用软件的特定过程对一致性类进行编程，否则可能以高速缓存的“跨步”运行。 或者，操作系统软件可以监视高速缓存中的存储器块的分配，并且提供程序指令以基于存储器块的分配来修改原始地址，以减少跨越。

公开(公告)号：US5996049A

公开(公告)日：1999-11-30

申请号：US839548

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0831

摘要： A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache. Upon sourcing the instruction or data value, the cache that originally contained the most recently accessed copy thereof changes its indication to indicate that its copy is now shared, and the processing unit which accessed the instruction or data value is thereafter indicated as having the cache containing the copy thereof that was most recently accessed. This protocol allows instructions and data values which are shared among several caches to be sourced directly (intervened) by the cache having the most recently accessed copy, without retrieval from system memory (RAM), significantly improving the processing speed of the computer system.

摘要翻译： 通过扩展现有技术的MESI高速缓存一致性协议以包括对应于最近访问状态的附加高速缓存入口状态，向多处理器计算机系统中的处理单元提供指令和数据值的方法。 处理单元的每个高速缓存具有至少一个具有用于存储指令或数据值的块的高速缓存行，并且提供了具有包含指令或数据值的块的高速缓存行处于“最近读取”状态的指示 。 每个缓存条目有三个位用于指示缓存条目的当前状态（五种可能状态之一）。 期望访问共享指令或数据值的处理单元检测来自具有最近访问的副本的高速缓存的指示的传输，并且指令或数据值来自该高速缓存。 在提供指令或数据值时，最初包含其最近访问的副本的高速缓存改变其指示以指示其副本现在被共享，并且访问该指令或数据值的处理单元此后被指示为具有高速缓存 最近访问的副本。 该协议允许由具有最近访问的副本的缓存直接（介入）在几个高速缓存之间共享的指令和数据值，而不从系统存储器（RAM）检索，显着地提高了计算机系统的处理速度。

公开(公告)号：US5983322A

公开(公告)日：1999-11-09

申请号：US839560

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08

CPC分类号： G06F12/0864

摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information. In this manner, a procedure running on the processor and allocating memory blocks to the cache such that the original addresses, if applied to the mapping function, would result in striding of the cache, runs more efficiently by using the encoded addresses to result in less striding of the cache.

摘要翻译： 公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。 逻辑单元连接到高速缓存，用于修改存储器设备中的存储器块的原始地址以产生编码的地址。 然后使用对编码的地址进行操作的映射函数来定义多个高速缓存一致等级，使得逻辑单元可以用于任意地将给定的一个原始地址分配给高速缓存一致性类别中的特定一个。 逻辑单元可以通过设置多个可编程字段来修改原始地址。 逻辑单元还可以收集关于高速缓存未命中的信息，并且响应于缓存未命中信息修改原始地址。 以这种方式，在处理器上运行的过程并将存储器块分配给高速缓存，使得原始地址（如果应用于映射功能）将导致高速缓存的跨越，则通过使用编码的地址来更有效地运行以导致较少的 跨越缓存。

公开(公告)号：US5958011A

公开(公告)日：1999-09-28

申请号：US829579

申请日：1997-03-31

申请人： Ravi Kumar Arimilli ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Jerry Don Lewis

IPC分类号： G06F11/30 ,  G06F13/14

CPC分类号： G06F13/423

摘要： A data processing system and method of communicating data in a data processing system are described. The data processing system includes a communication network to which a plurality of devices are coupled. At least one device among the plurality of devices coupled to the communication network includes mastering circuitry and snooping circuitry. According to the method, a first timing signal having a first frequency and a second timing signal having a second frequency different from the first frequency are generated. Communication transactions on the communication network are initiated utilizing the mastering circuitry, which operates in response to the first timing signal, and are monitored utilizing the snooping circuitry, which operates in response to the second timing signal.

摘要翻译： 描述了在数据处理系统中传送数据的数据处理系统和方法。 数据处理系统包括多个设备耦合到的通信网络。 耦合到通信网络的多个设备中的至少一个设备包括母盘制作电路和窥探电路。 根据该方法，产生具有第一频率的第一定时信号和具有与第一频率不同的第二频率的第二定时信号。 在通信网络上的通信交易是利用主控电路来启动的，该母盘控制电路响应于第一定时信号进行操作，并且利用响应于第二定时信号而工作的监听电路进行监视。

公开(公告)号：US5940611A

公开(公告)日：1999-08-17

申请号：US837519

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3824

摘要： A method and system for front-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. Multiple entries are provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a first entry of the front-end queue is filled completely. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry. In response to a determination that the address for the store instruction in the subsequent second entry is equal to the address for the store instruction in the first entry plus the byte count in the first entry, the store instruction in the subsequent second entry is collapsed into the store instruction in the first entry.

摘要翻译： 公开了一种用于处理器内存储指令前端收集的方法和系统。 根据本发明的方法和系统，数据处理系统内的存储队列包括前端队列和后端队列。 在后端队列中提供多个条目，每个条目包括地址字段，字节计数字段和数据字段。 首先确定前端队列的第一条目的数据字段是否被完全填充。 响应于确定前端队列的第一条目的数据字段未被完全填充，另外确定在后续第二条目中的存储指令的地址是否等于 第一个条目中的存储指令加上第一个条目中的字节数。 响应于确定后续第二条目中的存储指令的地址等于第一条目中的存储指令的地址加上第一条目中的字节计数，则随后的第二条目中的存储指令被折叠成 商店指令在第一个条目。

公开(公告)号：US5931924A

公开(公告)日：1999-08-03

申请号：US839437

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis ,  Derek Edward Williams

IPC分类号： G06F15/16 ,  G06F13/364 ,  G06F15/177 ,  G06F13/14

CPC分类号： G06F13/364

摘要： A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

摘要翻译： 描述了用于控制对数据处理系统中的共享资源的访问的方法和系统。 根据该方法，通过共享资源的多个请求者生成对资源的访问的多个请求。 每个请求者与优先级权重相关联，该权重指示相关请求者将被分配最高当前优先级的概率。 然后分配每个请求者相对于请求者的先前优先级基本随机确定的当前优先级。 为响应请求者的当前优先级，授予访问资源的请求。 在一个实施例中，与被许可的请求相对应的请求者用信号通知其请求已经被许可，并且与被拒绝的请求相对应的请求者用信号通知其请求未被授予。

公开(公告)号：US5893163A

公开(公告)日：1999-04-06

申请号：US992135

申请日：1997-12-17

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811

摘要： A method and system for allocating data among cache memories within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes a system memory and multiple processing units, wherein each of the processing units has a cache memory. The system memory is divided into a number of segments, wherein the number of segments is equal to the total number of cache memories. Each of these segments is represented by one of the cache memories such that a cache memory is responsible to cache data from its associated segment within the system memory.

摘要翻译： 公开了一种用于在对称多处理器数据处理系统内的高速缓存存储器中分配数据的方法和系统。 对称多处理器数据处理系统包括系统存储器和多个处理单元，其中每个处理单元具有高速缓冲存储器。 系统存储器被分成多个段，其中段的数量等于高速缓冲存储器的总数。 这些段中的每一个由高速缓冲存储器之一表示，使得高速缓冲存储器负责缓存来自系统存储器内的相关段的数据。

公开(公告)号：US5796979A

公开(公告)日：1998-08-18

申请号：US730994

申请日：1996-10-16

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F13/12

CPC分类号： G06F12/0866 ,  G06F12/0815 ,  G06F12/0835 ,  G06F2212/303

摘要： A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created. Individual writes within a cache line are gathered by the IOCC and only written to system memory when the I/O bus master accesses a different cache line or relinquishes the I/O bus.

摘要翻译： 数据处理系统包括处理器，系统存储器，一个或多个输入/输出通道控制器（IOCC）以及将处理器，存储器和IOCC连接在一起的系统总线，用于在各种元件之间传送指令，地址和数据 一个系统。 IOCC包括具有多行的分页缓存存储器，其中页面的每行可以是例如32字节。 缓存中的每个页面还具有该页面的几个属性位，包括所谓的WIM和属性位。 W位用于控制写操作; I位控制缓存抑制; M位控制存储器一致性。 由于IOCC不知道将这些页表属性位用于高速缓存行被DMA映射到系统内存，因此IOCC必须保持内存一致性和高速缓存一致性，而不会牺牲性能。 对于将DMA写入数据到系统内存，创建了称为全局，可高速缓存和基于需求的写入的新缓存属性。 高速缓存行中的单独写入由IOCC收集，只有当I / O总线主机访问不同的高速缓存行或放弃I / O总线时才写入系统存储器。

公开(公告)号：US06662216B1

公开(公告)日：2003-12-09

申请号：US08839478

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  Jerry Don Lewis

IPC分类号： G06F1516

CPC分类号： G06F11/349 ,  G06F12/0831 ,  G06F2201/885

摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.

摘要翻译： 根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。 多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。 响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。 根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。 指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。 响应于接收到高速缓存操作请求，确定是否更新状态指示。 响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。 状态指示随后被写回缓存目录。 因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

公开(公告)号：US06658556B1

公开(公告)日：2003-12-02

申请号：US09364288

申请日：1999-07-30

申请人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steve Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  Leo James Clark ,  John Steve Dodson ,  Guy Lynn Guthrie ,  Jerry Don Lewis

IPC分类号： G06F1730

CPC分类号： G06F9/3885 ,  G06F9/3013 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/384 ,  G06F9/3891

摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.

摘要翻译： 处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。 执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。 加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。