公开(公告)号：US06539625B2

公开(公告)日：2003-04-01

申请号：US09759017

申请日：2001-01-11

申请人： Brett H. Engel ,  Mark Hoinkis ,  John A. Miller ,  Soon-Cheon Seo ,  Yun-Yu Wang ,  Kwong Hon Wong

发明人： Brett H. Engel ,  Mark Hoinkis ,  John A. Miller ,  Soon-Cheon Seo ,  Yun-Yu Wang ,  Kwong Hon Wong

IPC分类号： H05K302

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Cr, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while maintaining low resistance.

公开(公告)号：US06417567B1

公开(公告)日：2002-07-09

申请号：US09482547

申请日：2000-01-13

申请人： Anthony G. Domenicucci ,  Lynne M. Gignac ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong ,  Roy A. Carruthers ,  Christian Lavoie ,  John A. Miller

发明人： Anthony G. Domenicucci ,  Lynne M. Gignac ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong ,  Roy A. Carruthers ,  Christian Lavoie ,  John A. Miller

IPC分类号： H01L2348

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/76856 ,  H01L2221/1078

摘要： A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

摘要翻译： 具有原子平坦界面的导电接触。 接触依次包括硅衬底，高度无序的硅化物层和氮氧化钛层。 硅化物层由钛，硅和元素钨，钽和钼之一形成。 硅衬底和硅化物层之间的界面是原子平坦的。 平面界面防止导电材料扩散到下面的硅衬底中。 该接触对于非常小的器件和浅接头是有用的，例如ULSI浅结点所需的。

公开(公告)号：US06388327B1

公开(公告)日：2002-05-14

申请号：US09756938

申请日：2001-01-09

申请人： Kenneth J. Giewont ,  Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Anthony G. Domenicucci ,  Craig Mitchell Ransom ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

发明人： Kenneth J. Giewont ,  Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Anthony G. Domenicucci ,  Craig Mitchell Ransom ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

摘要： A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.

摘要翻译： 描述了半导体结构的覆盖层。 覆盖层沉积在硅化物形成金属上，并且具有使得其中的氮扩散不足以引起下层硅上的氧化物层形成氧氮化物的组成。 覆盖层可以是不发生N扩散的金属层，或者包括Ti和/或TiN的一个或多个层，以使得N原子不到达氧化物层。 还描述了形成Ti和TiN层的方法。 通过在不足以引起目标上形成氮化物的氮气流中从Ti靶溅射而在N中沉积非化学计量的TiN是有利的。

公开(公告)号：US06387790B1

公开(公告)日：2002-05-14

申请号：US09602228

申请日：2000-06-23

申请人： Anthony Gene Domenicucci ,  Chung-Ping Eng ,  William Joseph Murphy ,  Tina J. Wagner ,  Yun-Yu Wang ,  Kwong Hon Wong

发明人： Anthony Gene Domenicucci ,  Chung-Ping Eng ,  William Joseph Murphy ,  Tina J. Wagner ,  Yun-Yu Wang ,  Kwong Hon Wong

IPC分类号： H01L213205

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76864

摘要： A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate; (b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; (c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region including a TiSi2 top layer and a CoSix bottom layer; and (d) optionally forming a conductive material on said Ti/TiN liner.

摘要翻译： 提供一种制造具有良好接触电阻和接触孔覆盖度的含Ti衬垫的方法。 将电离金属等离子体沉积的Ti的非晶区域转化成基本上结晶的区域的方法包括（a）提供其中形成有至少一个接触孔的结构，所述至少一个接触孔暴露至少一部分二硅化钴接触 形成在半导体衬底中; （b）通过电离金属等离子体沉积在所述至少一个接触孔中沉积Ti / TiN衬垫; （c）在有效使所述退火过程中形成的任何非晶区域再结晶成包括TiSi 2顶层和CoSix底层的结晶区域的条件下退火所述Ti / TiN衬垫; 和（d）任选地在所述Ti / TiN衬垫上形成导电材料。

公开(公告)号：US06383929B1

公开(公告)日：2002-05-07

申请号：US09759015

申请日：2001-01-11

申请人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

发明人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

摘要翻译： 在具有铜互连和低k层间电介质的集成电路中，通过使用第一内衬层Ti，随后是CVD TiN的共形内衬层，然后依次由 Ta或TaN的最终衬垫层，从而改善了通孔和下面的铜层之间的粘附性，同时将Ti和铜之间的合金化引起的电阻增加减少到可接受的量。