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129 条记录 (耗时 0.03 秒)

    Copper contact via structure using hybrid barrier layer
    4.
    发明授权
    Copper contact via structure using hybrid barrier layer 有权
    铜接触通孔结构使用混合阻挡层

    公开(公告)号：US07498256B2

    公开(公告)日：2009-03-03

    申请号：US11465865

    申请日：2006-08-21

    申请人： Randolph F. Knarr ,  Christopher D. Sheraw ,  Andrew H. Simon ,  Anna Topol ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    发明人： Randolph F. Knarr ,  Christopher D. Sheraw ,  Andrew H. Simon ,  Anna Topol ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/00

    CPC分类号： H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.

    摘要翻译： 公开了通过使用混合阻挡层的结构的接触。 一个接触通孔结构包括：通过电介质到硅化物区的开口; 与所述硅化物区直接接触的所述开口中的第一层，其中所述第一层选自：钛（Ti）和氮化钨（WN）; 在第一层上的至少一个第二层，选自氮化钽（TaN），氮化钛（TiN），钽（Ta），钌（Ru），铑（Rh），铑 铂（Pt）和钴（Co）; 铜（Cu）种子层; 和填充开口的剩余部分的铜（Cu）。

    Process for manufacturing a contact barrier
    6.
    发明授权
    Process for manufacturing a contact barrier 失效
    制造接触屏障的方法

    公开(公告)号：US06180521B2

    公开(公告)日：2001-01-30

    申请号：US09225598

    申请日：1999-01-06

    申请人： Patrick W. DeHaven ,  Anthony G. Domenicucci ,  Lynne M. Gignac ,  Glen L. Miles ,  Prabhat Tiwari ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

    发明人： Patrick W. DeHaven ,  Anthony G. Domenicucci ,  Lynne M. Gignac ,  Glen L. Miles ,  Prabhat Tiwari ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

    IPC分类号： H01L2128

    CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864

    摘要： A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

    摘要翻译： 一种用于形成具有平坦界面的导电触头的工艺。 将含有铌和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。通过该过程，硅化物和硅之间的平坦界面是 在退火时形成不太可能导致结漏电。 退火步骤还产生更均匀的双层，这是在随后的钨沉积期间防止钨侵蚀的更好的屏障。 还形成更大的硅化物晶粒，使得产生更少的晶界，减少晶界中的金属扩散。 该过程可用于形成非常小的器件和浅结的接触，例如当前和未来的半导体器件所需要的。

    Voltage sensitive resistor (VSR) read only memory
    7.
    发明授权
    Voltage sensitive resistor (VSR) read only memory 失效
    电压敏感电阻（VSR）只读存储器

    公开(公告)号：US08466443B2

    公开(公告)日：2013-06-18

    申请号：US12827197

    申请日：2010-06-30

    申请人： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    发明人： Terence L. Kane ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/02

    CPC分类号： H01L45/1616 ,  G11C17/14 ,  H01C7/1013 ,  H01C7/105 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.

    摘要翻译： 公开了一种包括半导体器件和连接到半导体器件的VSR的一次（WO）只读存储器（ROM）器件的电压敏感电阻器（VSR）。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流被施加到电阻时，可以变得更小的电阻性为102，更优选为103，最优选为104。 VSR。 多个VSR WO ROM器件可以被布置成在3-D堆栈中形成高密度可编程逻辑电路。 还公开了形成VSR WO ROM器件的方法。

    ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
    10.
    发明申请
    ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION 有权
    线路电路修改的抗结构

    公开(公告)号：US20110079874A1

    公开(公告)日：2011-04-07

    申请号：US12574926

    申请日：2009-10-07

    申请人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    发明人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5252 ,  H01L21/76823 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

    摘要翻译： 反熔丝结构和在反熔丝结构内形成接触的方法。 反熔丝结构包括具有上覆金属层的基板，形成在金属层的上表面上的电介质层，以及由通过电介质层蚀刻到金属层中的接触孔内的接触材料形成的接触。 接触通孔在接触通孔的底表面处包括金属材料，并且在金属材料的顶部上包​​括未处理或部分处理的金属前体。