公开(公告)号：US06388327B1

公开(公告)日：2002-05-14

申请号：US09756938

申请日：2001-01-09

申请人： Kenneth J. Giewont ,  Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Anthony G. Domenicucci ,  Craig Mitchell Ransom ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

发明人： Kenneth J. Giewont ,  Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Anthony G. Domenicucci ,  Craig Mitchell Ransom ,  Yun-Yu Wang ,  Horatio S. Wildman ,  Kwong Hon Wong

IPC分类号： H01L2348

CPC分类号： C23C14/0094 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855

摘要： A capping layer for a semiconductor structure is described. The capping layer is deposited over a silicide-forming metal and has a composition such that nitrogen diffusion therefrom is insufficient to cause formation of an oxynitride from an oxide layer on the underlying silicon. The capping layer may be a metal layer from which no N diffusion occurs, or one or more layers including Ti and/or TiN arranged so that N atoms do not reach the oxide layer. A method is also described for forming the Ti and TiN layers. It is advantageous to deposit non-stoichiometric TiN deficient in N, by sputtering from a Ti target in a nitrogen flow insufficient to cause formation of a nitride on the target.

摘要翻译： 描述了半导体结构的覆盖层。 覆盖层沉积在硅化物形成金属上，并且具有使得其中的氮扩散不足以引起下层硅上的氧化物层形成氧氮化物的组成。 覆盖层可以是不发生N扩散的金属层，或者包括Ti和/或TiN的一个或多个层，以使得N原子不到达氧化物层。 还描述了形成Ti和TiN层的方法。 通过在不足以引起目标上形成氮化物的氮气流中从Ti靶溅射而在N中沉积非化学计量的TiN是有利的。

公开(公告)号：US06323130B1

公开(公告)日：2001-11-27

申请号：US09515033

申请日：2000-03-06

申请人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

发明人： Stephen Bruce Brodsky ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Patricia Ann O'Neil ,  Yun Yu Wang

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).

摘要翻译： 一种在金属硅化物接触形成期间显着降低Si消耗和桥接的方法，包括以下步骤：（a）在含有电接触的电子器件的含硅衬底上形成金属硅合金层，所述合金层中的所述硅为 小于约30原子％，所述金属为Co，Ni或其混合物; （b）在约300℃至约500℃的温度下退火所述金属硅合金层，以便与所述金属硅合金或纯金属相比形成基本不可蚀刻的富金属硅化物层; （c）在非硅区域上有选择地去除任何未反应的金属硅合金; 和（d）在有效形成处于其最低电阻相的金属硅化物相的条件下退火所述富金属硅化物层。 可以在退火步骤（b）之前在金属硅合金层上形成任选的氧阻挡层。

公开(公告)号：US5923999A

公开(公告)日：1999-07-13

申请号：US741159

申请日：1996-10-29

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US6049131A

公开(公告)日：2000-04-11

申请号：US887786

申请日：1997-07-03

申请人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

发明人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

IPC分类号： C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/76897 ,  C23C16/04 ,  H01L21/28061 ,  H01L21/28562 ,  H01L29/66515

摘要： A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g., worm holes), poor adhesion, uncontrolled selectivity and uneven morphology.

摘要翻译： 公开了通过在暴露的硅上而不是场氧化物上的选择性难熔金属生长/沉积的方法制备的方法和装置。 该方法包括在DHF浸渍中预处理晶片，随后是以下步骤：1）通过使难熔金属卤化物与所述硅衬底的暴露表面反应来选择性地将难熔金属沉积在硅衬底的暴露表面上; 2）通过使难熔金属卤化物与含硅气体反应来限制硅衬底的消耗; 和3）通过使难熔金属卤化物与氢反应来进一步增加难熔金属厚度。 通过适当的预处理和选择参数1）温度; 2）压力; 3）时间; 4）流程和5）每个沉积步骤中的流量比，本发明充分地解决了不均匀的n +与p +（源/漏）生长，难熔金属深入/侵入硅区域（例如蠕虫孔）的困难， 粘附性差，不受控制的选择性和不均匀的形态。

公开(公告)号：US6114736A

公开(公告)日：2000-09-05

申请号：US351808

申请日：1999-07-12

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L23/283

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US5690795A

公开(公告)日：1997-11-25

申请号：US463463

申请日：1995-06-05

申请人： Michael Rosenstein ,  Howard Grunes ,  Stephen Bruce Brodsky

发明人： Michael Rosenstein ,  Howard Grunes ,  Stephen Bruce Brodsky

IPC分类号： C23C14/00 ,  C23C14/56 ,  H01L21/00 ,  H01L21/203 ,  H01L21/302 ,  H01L21/3065 ,  C23C14/34 ,  C23C16/00 ,  C23F1/02

CPC分类号： H01L21/67017 ,  C23C14/564 ,  Y10S156/916

摘要： A structure and method is described for securing an overspray shield in processing chambers in the wall sandwich of the chamber or using a dimensionally compliant floating spacer ring to elastically clamp the overspray shield in position in a vacuum substrate processing chamber without the use of removable fasteners. The configuration uses the differential pressures between the inside and outside of the chamber to clamp the overspray shield along with its shield clamping assembly components at a spacer position in the chamber. The spacer position is generally interior to vacuum sealing limits of the chamber. The arrangement is such that if misalignment occurs a good vacuum-type seal cannot be achieved unless the parts are moved to correct alignment. When correctly aligned the overspray shield is tightly held to the processing chamber wall and electrical continuity between the processing chamber wall and the overspray shield is assured throughout expected process conditions.

摘要翻译： 描述了一种结构和方法，用于将过喷屏蔽件固定在室的壁三明治中的处理腔室中，或者使用尺寸合适的浮动间隔环来弹性地将超喷射屏蔽件弹性地夹紧在真空基板处理室中的适当位置，而不使用可移除的紧固件。 该配置使用腔室内部和外部之间的压差将过喷面罩与其屏蔽夹紧组件部件一起夹在腔室中的间隔件位置。 间隔件位置通常在腔室的真空密封极限内部。 这种布置使得如果发生不对准，则不能实现良好的真空型密封，除非将部件移动到正确的对准。 当正确对准时，超喷射屏蔽被紧紧地保持在处理室壁上，并且在预期的工艺条件下确保了处理室壁和过喷面罩之间的电连续性。

公开(公告)号：US06440808B1

公开(公告)日：2002-08-27

申请号：US09672185

申请日：2000-09-28

申请人： Diane Catherine Boyd ,  Stephen Bruce Brodsky ,  Hussein Ibrahim Hanafi ,  Ronnen Andrew Roy

发明人： Diane Catherine Boyd ,  Stephen Bruce Brodsky ,  Hussein Ibrahim Hanafi ,  Ronnen Andrew Roy

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  Y10S438/926

摘要： A sub-0.1 &mgr;m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

摘要翻译： 利用镶嵌栅极工艺提供了具有最小多晶硅耗尽，水银源和漏极结以及非常低的薄层电阻多晶硅栅极的0.1微米MOSFET器件，其中源极和漏极注入激活退火和硅化物在存在虚拟的情况下发生 栅极区域，其后被去除并被多晶硅栅极区域替代。

公开(公告)号：US5807788A

公开(公告)日：1998-09-15

申请号：US753128

申请日：1996-11-20

申请人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

发明人： Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Seshadri Subbanna

IPC分类号： C23C16/04 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/76897 ,  C23C16/04 ,  H01L21/28061 ,  H01L21/28562 ,  H01L29/66515

摘要： A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively depositing a refractory metal on the exposed surfaces of the silicon substrate by reacting a refractory metal halide with the exposed surfaces of said silicon substrate; 2) limiting silicon substrate consumption by reacting the refractory metal halide with a silicon containing gas; and 3) further increasing the refractory metal thickness by reacting the refractory metal halide with hydrogen. Through an adequate pretreatment and selection of the parameters of 1) temperature; 2) pressure; 3) time; 4) flow and 5) flow ratio during each of the deposition steps, this invention adequately addresses the difficulties of uneven n+ versus p+ (source/drain) growth, deep consumption/encroachment by the refractory metal into silicon regions (e.g., worm holes), poor adhesion, uncontrolled selectivity and uneven morphology.

摘要翻译： 公开了通过在暴露的硅上而不是场氧化物上的选择性难熔金属生长/沉积的方法制备的方法和装置。 该方法包括在DHF浸渍中预处理晶片，随后是以下步骤：1）通过使难熔金属卤化物与所述硅衬底的暴露表面反应来选择性地将难熔金属沉积在硅衬底的暴露表面上; 2）通过使难熔金属卤化物与含硅气体反应来限制硅衬底的消耗; 和3）通过使难熔金属卤化物与氢反应来进一步增加难熔金属厚度。 通过适当的预处理和选择参数1）温度; 2）压力; 3）时间; 4）流程和5）每个沉积步骤中的流量比，本发明充分地解决了不均匀的n +与p +（源/漏）生长，难熔金属深入/侵入硅区域（例如蠕虫孔）的困难， 粘附性差，不受控制的选择性和不均匀的形态。