公开(公告)号：US5506807A

公开(公告)日：1996-04-09

申请号：US393004

申请日：1995-03-03

Applicant: Richard Ferrant ,  Lysiane Koechlin

Inventor： Richard Ferrant ,  Lysiane Koechlin

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/848

Abstract: A novel redundancy architecture for an integrated-circuit memory is utilized having no redundancy columns separate from the useful columns but with each useful column, except for the first column, serving as a redundancy column for any adjacent defective column. If a column of order j, normally designated by an output of order j of the column decoder DC, is serviceable, it is actually this column which will be selected by the corresponding output of the decoder DC. On the other hand, if the column is defective, no specialized remote redundancy column will be sought for the repair but instead the output of the decoder will be made to select the following column (order j+1), which would normally have been designated by the following output (order j+1) of the decoder. The other decoder output will be routed towards a third column (order j+2), etc. Therefore, the links between the decoder outputs and the column used will be progressively offset. The memory plane is seen in groups of n+1 columns with the row DR and column DC decoders. A fuse circuit CF designates a defective column. Through the use of this architecture all of the columns can be tested even those which are not being used.

Abstract translation: 利用集成电路存储器的新型冗余架构，其中没有与有用列分离的冗余列，而是除了第一列之外的每个有用列，用作任何相邻有缺陷列的冗余列。 如果通常由列解码器DC的阶数j的输出指定的阶数j可用，则实际上该列将由解码器DC的相应输出选择。 另一方面，如果列有故障，则不会寻求专门的远程冗余列进行修复，而是将解码器的输出选择通常已经被指定的以下列（第j + 1号） 通过解码器的以下输出（顺序j + 1）。 其他解码器输出将被路由到第三列（订单j + 2）等。因此，解码器输出和所使用的列之间的链接将逐渐偏移。 存储器平面被看作是具有行DR和列直流解码器的n + 1列的组。 保险丝电路CF表示有缺陷的列。 通过使用这种架构，即使是那些未被使用的列，也可以测试所有的列。

公开(公告)号：US4879693A

公开(公告)日：1989-11-07

申请号：US128169

申请日：1987-12-03

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407

CPC classification number: G11C7/1057 ,  G11C7/1006 ,  G11C7/1051

Abstract: A self-synchronization device is disclosed for output circuits comprising a "3-state" gate of memories working in internal clock mode. This device consists of a sequential logic circuit which allows the "3-state" gate to go into low impedance only when a datum is available at the output of the read amplifiers.

Abstract translation: 公开了一种用于输出电路的自同步装置，其包括以内部时钟模式工作的存储器的“3态”门。 该器件由顺序逻辑电路组成，只有当读取放大器的输出端的数据可用时，才允许“3态”门进入低阻抗。

公开(公告)号：US4877483A

公开(公告)日：1989-10-31

申请号：US212889

申请日：1988-06-29

Applicant: Albert Bergemont ,  Richard Ferrant

Inventor： Albert Bergemont ,  Richard Ferrant

IPC: H01L23/522 ,  H01L21/31 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC classification number: H01L21/76834

Abstract: A method of contact between two conductive or semiconductive layers deposited on a substrate is disclosed. The method comprises the following steps:the depositing and etching of a first layer,the depositing of an insulating layer under pressure and temperature conditions such that the insulating layer is thinned at the edges of the etched zones of the first layer as compared with the thickness on the surface of the substrate and on the surfaces of the etched zones of the first layer,the chemical etching of the insulating layer on a thickness at least equal to the thickness of the thinned layer but substantially smaller than the thickness elsewhere,the depositing and etching of the second conductive or semiconductive layer under pressure and temperature conditions leading to high covering capacity.

Abstract translation: 公开了沉积在基底上的两个导电或半导体层之间的接触方法。 该方法包括以下步骤：沉积和蚀刻第一层，在压力和温度条件下沉积绝缘层，使得绝缘层在第一层的蚀刻区域的边缘处变薄，与厚度 在衬底的表面上和第一层的蚀刻区域的表面上，绝缘层的化学蚀刻的厚度至少等于薄层的厚度，但是基本上小于其他地方的厚度，沉积和 在导致高覆盖能力的压力和温度条件下蚀刻第二导电层或半导体层。

公开(公告)号：US09035474B2

公开(公告)日：2015-05-19

申请号：US12793515

申请日：2010-06-03

Applicant: Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.

Abstract translation: 本发明涉及一种制造半导体衬底的方法，特别是通过提供一个施主衬底和一个把手衬底来制造绝缘体上半导体衬底，通常形成一个或多个掺杂区域的图案，通常在处理衬底内部，然后附着 例如通过分子结合施主衬底和处理衬底以获得施主手柄化合物。

公开(公告)号：US08455938B2

公开(公告)日：2013-06-04

申请号：US12886421

申请日：2010-09-20

Applicant: Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

Inventor： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC: H01L29/788 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

Abstract: The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

Abstract translation: 本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。 本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属 或半导体层，以及去除掩模和/或图案层。

公开(公告)号：US08325506B2

公开(公告)日：2012-12-04

申请号：US12974916

申请日：2010-12-21

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C15/00

CPC classification number: G11C15/046 ,  H04L45/7453

Abstract: The invention provides a content-addressable memory cell formed by two transistors that are configured so that one of the transistors is for storing a data bit and the other for is storing the complement of the data bit. Each transistor has a back control gate that can be controlled to block the associated transistor. The device also includes a comparison circuit that is configured to operate the first and second transistors in read mode while controlling the back control gate of each of the transistors so as to block the passing transistor if a proposed bit and the stored bit correspond. Then, the presence or absence of current on a source line linked to the source of each of the transistors indicates whether the proposed bit and the stored bit are identical or not. The invention also provides methods for operating the content-addressable memory cells of this invention, as well as content-addressable memories having a plurality of the content-addressable memory cells of this invention.

Abstract translation: 本发明提供一种由两个晶体管形成的可内容寻址的存储单元，其被配置为使晶体管中的一个用于存储数据位，而另一个用于存储数据位的补码。 每个晶体管具有可控制的阻挡相关晶体管的反向控制栅极。 该器件还包括比较电路，其被配置为在读取模式下操作第一和第二晶体管，同时控制每个晶体管的反向控制栅极，以便如果所提出的位和存储的位对应，则阻止通过晶体管。 然后，连接到每个晶体管的源极的源极线上的电流的存在或不存在指示所提出的位和存储的位是否相同。 本发明还提供了用于操作本发明的内容可寻址存储器单元的方法，以及具有多个本发明的可内容寻址存储单元的可内容寻址存储器。

公开(公告)号：US20120275253A1

公开(公告)日：2012-11-01

申请号：US13456047

申请日：2012-04-25

Applicant: Richard Ferrant ,  Roland Thewes

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C2207/002

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors.

Abstract translation: 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端， 以及具有连接到第二位线的输出和连接到第一位线的输入的第二CMOS反相器。 每个CMOS反相器包括上拉晶体管和下拉晶体管，并且读出放大器具有一对传输栅晶体管，被布置为将第一和第二位线连接到第一和第二全局位线。 有利的是，栅极晶体管由上拉晶体管或上拉晶体管构成。

公开(公告)号：US20120275252A1

公开(公告)日：2012-11-01

申请号：US13456020

申请日：2012-04-25

Applicant: Richard Ferrant ,  Roland Thewes

Inventor： Richard Ferrant ,  Roland Thewes

IPC: G11C7/12 ,  G11C7/02

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

Abstract translation: 一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端 位线和具有连接到第二位线（/ BL）的输出的第二CMOS反相器和连接到第一位线的输入。 每个CMOS反相器包括上拉和下拉晶体管，其中上拉晶体管或下拉晶体管中的任一个的源极电耦合并连接到上拉电压源或下拉电压源，而没有 在晶体管的源极和电压源之间的中间晶体管。

公开(公告)号：US08223582B2

公开(公告)日：2012-07-17

申请号：US12793553

申请日：2010-06-03

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

Abstract translation: 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US20110170343A1

公开(公告)日：2011-07-14

申请号：US12942754

申请日：2010-11-09

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C11/40 ,  H01L29/786

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0711 ,  H01L27/10802 ,  H01L29/086 ,  H01L29/7302

Abstract: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

Abstract translation: 本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。 注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。 具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。 本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。