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    SRAM-type memory cell
    1.
    发明授权
    SRAM-type memory cell 有权
    SRAM型存储单元

    公开(公告)号：US08575697B2

    公开(公告)日：2013-11-05

    申请号：US13039167

    申请日：2011-03-02

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： H01L27/11 ,  H01L27/12 ,  G11C5/06 ,  G11C11/00

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

    摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

    摘要翻译： 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

    Pseudo-inverter circuit on SeOI
    3.
    发明授权
    Pseudo-inverter circuit on SeOI 有权
    SeOI上的伪逆变电路

    公开(公告)号：US08654602B2

    公开(公告)日：2014-02-18

    申请号：US13495632

    申请日：2012-06-13

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

    摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

    摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

    PSEUDO-INVERTER CIRCUIT ON SeO1
    4.
    发明申请
    PSEUDO-INVERTER CIRCUIT ON SeO1 有权
    PSO1上的PSEUDO-INVERTER电路

    公开(公告)号：US20110242926A1

    公开(公告)日：2011-10-06

    申请号：US12793553

    申请日：2010-06-03

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： G11C8/08 ,  G05F1/10

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

    摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

    摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

    Nano-sense amplifier
    5.
    发明授权
    Nano-sense amplifier 有权
    纳米读出放大器

    公开(公告)号：US08358552B2

    公开(公告)日：2013-01-22

    申请号：US12789100

    申请日：2010-05-27

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

    摘要： A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

    摘要翻译： 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

    NANO-SENSE AMPLIFIER
    6.
    发明申请
    NANO-SENSE AMPLIFIER 有权
    NANO-SENSE放大器

    公开(公告)号：US20110222361A1

    公开(公告)日：2011-09-15

    申请号：US12789100

    申请日：2010-05-27

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： G11C7/06

    CPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

    摘要： A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

    摘要翻译： 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

    Device comprising a field-effect transistor in a silicon-on-insulator
    8.
    发明授权
    Device comprising a field-effect transistor in a silicon-on-insulator 有权
    装置包括绝缘体上硅中的场效应晶体管

    公开(公告)号：US08455938B2

    公开(公告)日：2013-06-04

    申请号：US12886421

    申请日：2010-09-20

    申请人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

    发明人： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

    IPC分类号： H01L29/788 ,  H01L27/12

    CPC分类号： H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

    摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

    摘要翻译： 本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。 本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属 或半导体层，以及去除掩模和/或图案层。

    Pseudo-inverter circuit on SeOI
    9.
    发明授权
    Pseudo-inverter circuit on SeOI 有权
    SeOI上的伪逆变电路

    公开(公告)号：US08223582B2

    公开(公告)日：2012-07-17

    申请号：US12793553

    申请日：2010-06-03

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

    摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

    摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

    Pseudo-inverter circuit with multiple independent gate transistors
    10.
    发明授权
    Pseudo-inverter circuit with multiple independent gate transistors 有权
    具有多个独立栅极晶体管的伪逆变器电路

    公开(公告)号：US09496877B2

    公开(公告)日：2016-11-15

    申请号：US14346270

    申请日：2011-09-30

    申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

    IPC分类号： H03K19/20 ,  G11C8/08 ,  G11C11/408

    CPC分类号： H03K19/20 ,  G11C8/08 ,  G11C11/4085

    摘要： The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).

    摘要翻译： 本发明涉及一种电路，其包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管 第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作 （G2p，G2N）。