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51.发明申请INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权信息处理系统，具有立即调度在双存储单元缓存中的负载运算，具有单个分配到写/读数据流公开(公告)号：US20100268890A1
公开(公告)日：2010-10-21
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。
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52.发明申请Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory 有权信息处理系统，即时调度负载操作和细粒度访问高速缓存公开(公告)号：US20100268883A1
公开(公告)日：2010-10-21
申请号：US12424332
申请日：2009-04-15
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。 控制逻辑确定每个加载操作或存储操作的大小要求。 当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。
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53.发明申请METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权用于链接更多有效存储队列使用的多个小型存储队列的方法公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译： 数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。 存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。 存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。 响应于第一段不等于第二段，第一个条目链接到第二个条目。
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公开(公告)号：US07490202B2
公开(公告)日：2009-02-10
申请号：US11956112
申请日：2007-12-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
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55.发明授权公开(公告)号：US07490200B2
公开(公告)日：2009-02-10
申请号：US11054924
申请日：2005-02-10
IPC分类号： G06F12/08
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry. The cache array may be arranged with rows and columns of cache sectors wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array outputs different sectors of the given cache line in successive clock cycles based on the latency of a given sector.
摘要翻译： 高速缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分割成至少两个切片，并且使用第一高速缓存目录访问第一高速缓存阵列切片，同时使用第二高速缓存目录来访问第二高速缓存阵列切片，但是访问 从缓存目录中使用单个缓存仲裁器来管理单个访问/命令端口。 在说明性实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与缓存仲裁器通信。 与处理器核心相关联的地址标签被从处理器核心以指定的位发送，指定的位将地址标签与只有一个高速缓存阵列片相关联，其相应的目录确定地址标签是否与当前有效的高速缓存条目匹配。 高速缓存阵列可以布置有高速缓存扇区的行和列，其中给定的高速缓存行分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列和另一个 给定高速缓存行的一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。
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56.发明授权Half-good mode for large L2 cache array topology with different latency domains 有权具有不同延迟域的大型L2缓存阵列拓扑的半好模式公开(公告)号：US07308537B2
公开(公告)日：2007-12-11
申请号：US11055262
申请日：2005-02-10
CPC分类号： G06F12/0851 , G06F12/126
摘要： A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes). The cache array may be arranged with rows and columns of cache sectors (rows corresponding to the cache ways) wherein a given cache line is further spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array can also output different sectors of the given cache line in successive clock cycles based on the latency of a given sector.
摘要翻译： 高速缓存存储器将高速缓存阵列逻辑地分区成至少两个切片，每个切片具有多个高速缓存行，其中给定的高速缓存行分布在连续字节的两个或多个高速缓存路径上以及在两个高速缓存片之间共享的给定高速缓存路径，如果 一个缓存方式是缺陷，其是第一高速缓存片中的第一高速缓存行和第二高速缓存片中的第二高速缓存行的一部分的一部分，其被禁用，同时继续使用至少另一种其他缓存方式，其也是 第一个缓存行和第二个缓存行的一部分。 在说明性实施例中，高速缓存阵列被设置为关联性，并且给定高速缓存行的至少两个不同的高速缓存路径包含该高速缓存行的不同的一致类。 可以通过防止驱逐机制以有缺陷的方式分配任何一致类来禁用缺陷缓存方式。 例如，可以禁用一半的高速缓存行（即，一致等级的一半）。 高速缓存阵列可以被布置成具有行和列的高速缓存扇区（对应于高速缓存路线的行），其中给定高速缓存行进一步分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于 具有第一延迟的第一列和给定高速缓存行的另一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列还可以基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。
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公开(公告)号：US07272664B2
公开(公告)日：2007-09-18
申请号：US10313330
申请日：2002-12-05
IPC分类号： G06F15/16 , G06F15/167 , G06F15/00 , G06F15/76
CPC分类号： G06F9/4812 , G06F9/30116 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.
摘要翻译： 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器访问数据处理系统中的任何处理器，用于将处理器的处理状态存储到存储器中，而与处理器上运行的操作系统无关。
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58.发明授权Processor virtualization mechanism via an enhanced restoration of hard architected states 失效处理器虚拟化机制通过增强硬件架构状态的恢复公开(公告)号：US06981083B2
公开(公告)日：2005-12-27
申请号：US10313320
申请日：2002-12-05
CPC分类号： G06F9/30116 , G06F9/462
摘要： A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.
摘要翻译： 公开了一种用于从等待执行的空闲进程池预加载下一个进程的硬结构状态的方法和系统。 当执行过程在处理器上中断时，下一个进程已被预先存储在处理器中的硬设计状态被加载到处理器中的架构存储位置。 基于分配给等待处理的优先级来确定要执行的下一个进程，并因此其预先存储在处理器中的相应的硬设计状态。
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59.发明授权High speed lock acquisition mechanism with time parameterized cache coherency states 有权具有时间参数化高速缓存一致性状态的高速锁定采集机制公开(公告)号：US06629212B1
公开(公告)日：2003-09-30
申请号：US09437187
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently “bounce” between multiple processors, which causes a significant reduction in cache efficiency. The preferred embodiment provides a modified MESI state which holds the status of the cache line static for a fixed period of time, which eliminates the bounce effect from contention between multiple processors.
摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 在使用MESI方法的常规系统中，两个或多个处理器通常将竞争公用高速缓存行的所有权。 因此，高速缓存行的所有权将在多个处理器之间频繁地“反弹”，这导致高速缓存效率的显着降低。 优选实施例提供修改的MESI状态，其将高速缓存行的状态保持固定的固定时间段，从而消除了来自多个处理器之间的争用的反弹效应。
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公开(公告)号：US06549989B1
公开(公告)日：2003-04-15
申请号：US09437184
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.
摘要翻译： 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。 特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。 优选实施例提供了附加高速缓存状态，其特别地指示处理器在执行任何必要的修改之后已经在高速缓存线上释放其锁定。
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