公开(公告)号：US20150137119A1

公开(公告)日：2015-05-21

申请号：US14570565

申请日：2014-12-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro SAKATA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L29/08 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract translation: 本发明的目的是提供一种包括具有稳定电特性的薄膜晶体管的高度可靠的半导体器件。 在包括半导体层为氧化物半导体层的反交错薄膜晶体管的半导体器件中，在氧化物半导体层上设置有缓冲层。 缓冲层与半导体层的沟道形成区域和源极和漏极电极层接触。 缓冲层的膜具有电阻分布。 设置在半导体层的沟道形成区域上的区域具有比半导体层的沟道形成区域更低的导电性，并且与源极和漏极电极层接触的区域具有比半导体的沟道形成区域更高的导电性 层。

公开(公告)号：US20150041801A1

公开(公告)日：2015-02-12

申请号：US14447875

申请日：2014-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takuya HIROHASHI ,  Masahiro TAKAHASHI ,  Motoki NAKASHIMA ,  Ryosuke WATANABE ,  Masashi TSUBUKU

IPC: H01L29/792 ,  H01L29/24

CPC classification number: H01L29/792 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes a semiconductor layer, a gate electrode overlapping with the semiconductor layer, a first gate insulating layer between the semiconductor layer and the gate electrode, and a second gate insulating layer between the first gate insulating layer and the gate electrode. The first gate insulating layer includes an oxide in which the nitrogen content is lower than or equal to 5 at. %, and the second gate insulating layer includes charge trap states.

Abstract translation: 半导体器件包括半导体层，与半导体层重叠的栅极电极，在半导体层和栅电极之间的第一栅极绝缘层，以及位于第一栅极绝缘层和栅电极之间的第二栅极绝缘层。 第一栅极绝缘层包括其中氮含量低于或等于5at的氧化物。 ％，第二栅极绝缘层包括电荷陷阱状态。

公开(公告)号：US20140291675A1

公开(公告)日：2014-10-02

申请号：US14305156

申请日：2014-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro SAKATA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract translation: 本发明的目的是提供一种包括具有稳定电特性的薄膜晶体管的高度可靠的半导体器件。 在包括半导体层为氧化物半导体层的反交错薄膜晶体管的半导体器件中，在氧化物半导体层上设置有缓冲层。 缓冲层与半导体层的沟道形成区域和源极和漏极电极层接触。 缓冲层的膜具有电阻分布。 设置在半导体层的沟道形成区域上的区域具有比半导体层的沟道形成区域更低的导电性，并且与源极和漏极电极层接触的区域具有比半导体的沟道形成区域更高的导电性 层。

公开(公告)号：US20140193946A1

公开(公告)日：2014-07-10

申请号：US14202670

申请日：2014-03-10

Applicant: Semiconductor Energy Laboratory Co, Ltd.

Inventor： Shunpei YAMAZAKI ,  Takuya HIROHASHI ,  Masahiro TAKAHASHI ,  Takashi SHIMAZU

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02502 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

Abstract translation: 可以使用较大的衬底，并且可以通过形成具有高结晶度的氧化物半导体层来制造具有期望的高场敏性迁移率的晶体管，由此大尺寸显示装置，高性能半导体器件， 等可以投入实际使用。 在衬底上形成第一多组分氧化物半导体层，并在其上形成单组分氧化物半导体层; 然后通过在500℃至1000℃（包括端值）进行热处理从表面向内部进行晶体生长，优选550℃至750℃，从而使第一多组分氧化物半导体层 包括单晶区域和形成包括单晶区域的单组分氧化物半导体层; 并且包括单晶区域的第二多分量氧化物半导体层堆叠在包括单晶区域的单组分氧化物半导体层上。