公开(公告)号：US20240254616A1

公开(公告)日：2024-08-01

申请号：US18633854

申请日：2024-04-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/34 ,  B28B11/24 ,  C04B35/453 ,  C04B35/64 ,  C23C14/08 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

CPC classification number: C23C14/3414 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C23C14/08 ,  C23C14/086 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

公开(公告)号：US20240250183A1

公开(公告)日：2024-07-25

申请号：US18626592

申请日：2024-04-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1343 ,  H01L21/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H10K59/121

CPC classification number: H01L29/7869 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78696 ,  G02F2202/10 ,  H01L21/02565 ,  H10K59/1213

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US20190237585A1

公开(公告)日：2019-08-01

申请号：US16381479

申请日：2019-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G02F1/1337 ,  H01L29/24 ,  H01L29/51 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/66 ,  H01L29/04 ,  G02F1/1339 ,  G02F1/1343

CPC classification number: H01L29/7869 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  G02F2202/10 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78696

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US20180145153A1

公开(公告)日：2018-05-24

申请号：US15856763

申请日：2017-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takuya HIROHASHI ,  Masahiro TAKAHASHI ,  Takashi SHIMAZU

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/66742 ,  H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02502 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

公开(公告)号：US20170148925A1

公开(公告)日：2017-05-25

申请号：US15422945

申请日：2017-02-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/04 ,  G02F1/1339 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1337 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  G02F2202/10 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78696

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US20160056299A1

公开(公告)日：2016-02-25

申请号：US14931224

申请日：2015-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: A decrease in on-state current in a semiconductor device including an oxide semiconductor film is suppressed. A transistor including an oxide semiconductor film, an insulating film which includes oxygen and silicon, a gate electrode adjacent to the oxide semiconductor film, the oxide semiconductor film provided to be in contact with the insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the interface with the insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region.

公开(公告)号：US20140113687A1

公开(公告)日：2014-04-24

申请号：US14139892

申请日：2013-12-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro SAKATA ,  Takashi SHIMAZU ,  Hiroki OHARA ,  Toshinari SASAKI ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H04M1/02

CPC classification number: H01L29/78696 ,  C23C14/086 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02592 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78693 ,  H04M1/0266

Abstract: A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.

Abstract translation: 一种包括具有氧化物半导体层并具有高电特性和可靠性的薄膜晶体管的半导体器件。 通常使用包含绝缘体（绝缘氧化物，绝缘氮化物，氮氧化硅，氮氧化铝等）（通常为SiO 2）的氧化物半导体靶进行膜沉积，使得其中Si元素浓度在厚度 氧化物半导体层的方向具有根据与栅电极的距离的增加而增加的梯度。

公开(公告)号：US20230420570A1

公开(公告)日：2023-12-28

申请号：US18244329

申请日：2023-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24 ,  H01L29/51 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78696 ,  H01L21/02565

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US20190185986A1

公开(公告)日：2019-06-20

申请号：US16285297

申请日：2019-02-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/08 ,  C23C14/34 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  C04B35/453 ,  B28B11/24 ,  C04B35/64

CPC classification number: C23C14/08 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

公开(公告)号：US20170016108A1

公开(公告)日：2017-01-19

申请号：US15189104

申请日：2016-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  C23C14/34 ,  H01L21/02

CPC classification number: C23C14/08 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

Abstract translation: 已经有使用氧化物半导体形成的晶体管的可靠性与使用非晶硅形成的晶体管的可靠性差。 因此，在本发明中，制造了包括使用氧化物半导体形成的高可靠性晶体管的半导体器件。 使用包含具有结晶性的氧化物半导体的溅射靶，通过溅射法沉积氧化物半导体膜，并且其中晶体的c轴方向平行于氧化物半导体的顶表面的法向矢量。 通过混合原料形成靶，使其组成比可以得到晶体结构。