公开(公告)号：US11258358B2

公开(公告)日：2022-02-22

申请号：US16742248

申请日：2020-01-14

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Shivam Kalla

IPC: H02M3/07

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.

公开(公告)号：US10811960B2

公开(公告)日：2020-10-20

申请号：US16563069

申请日：2019-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  G05F1/10 ,  H03K19/096

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US20190028024A1

公开(公告)日：2019-01-24

申请号：US15652447

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  H03K3/356

Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.

公开(公告)号：US09659933B2

公开(公告)日：2017-05-23

申请号：US14697461

申请日：2015-04-27

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Amit Chhabra

IPC: H03K17/693 ,  H01L27/092 ,  H01L27/12 ,  H03K17/00

CPC classification number: H03K17/693 ,  H01L27/092 ,  H01L27/1203 ,  H03K17/005 ,  H03K2217/0018

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

公开(公告)号：US12094542B2

公开(公告)日：2024-09-17

申请号：US17542323

申请日：2021-12-03

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Neha Dalal

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

公开(公告)号：US11764673B2

公开(公告)日：2023-09-19

申请号：US17673033

申请日：2022-02-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07

CPC classification number: H02M3/071

Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

公开(公告)号：US11031865B2

公开(公告)日：2021-06-08

申请号：US16911967

申请日：2020-06-25

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07

Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.

公开(公告)号：US10461636B2

公开(公告)日：2019-10-29

申请号：US16162668

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  G05F1/10 ,  H03K19/096

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US20190123638A1

公开(公告)日：2019-04-25

申请号：US16162668

申请日：2018-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  G05F1/10 ,  H03K19/096

CPC classification number: H02M3/07 ,  G05F1/10 ,  H02M2003/078 ,  H03K19/096

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US20190028026A1

公开(公告)日：2019-01-24

申请号：US15652748

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Abhishek Mittal

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/071

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.