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51.发明授权Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor 有权在执行处理器中避免写后危害的方法和装置公开(公告)号：US07263603B2
公开(公告)日：2007-08-28
申请号：US10923219
申请日：2004-08-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30189 , G06F9/383 , G06F9/3838 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instructions in a speculative-execution mode. The system also maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.
摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免写后读取（RAW）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到停顿状态时，系统生成检查点，并以推测执行模式执行指令和后续指令。 该系统还维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 系统使用这种依赖信息来避免在推测执行模式下的RAW危害。
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52.发明授权公开(公告)号：US07257700B2
公开(公告)日：2007-08-14
申请号：US11053382
申请日：2005-02-07
IPC分类号： G06F9/48
CPC分类号： G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode. Upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the system uses the checkpoint to resume execution in the normal-execution mode from the launch-point instruction. In doing so, the system ensures that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for in order to prevent register RAW hazard when resuming execution from the launch-point instruction.
摘要翻译： 本发明的一个实施例提供一种从推测执行模式返回时避免寄存器读写（RAW）危险的系统。 该系统在具有按顺序架构的处理器内操作，其中处理器包括短延迟记分板，其延迟取决于未完成的短延迟指令的指令的发布。 在操作期间，在正常执行模式下执行程序期间，系统以程序顺序发出执行指令。 在发生指令（发射点指令）期间遇到使处理器进入推测执行模式的条件（发射条件）时，系统产生检查点，该检查点随后可用于将程序的执行返回到 启动点指令，并以推测执行模式开始执行。 当遇到导致处理器离开推测执行模式并返回到启动点指令的条件时，系统使用检查点从启动点指令以正常执行模式恢复执行。 在这样做时，系统确保在进入投机执行模式之前处于短延迟记分板中的条目，以及尚未解决的条目，以便在从启动时恢复执行时防止寄存器RAW危险， 点指令。
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53.发明授权Selective execution of deferred instructions in a processor that supports speculative execution 有权在支持推测执行的处理器中选择性执行延迟指令公开(公告)号：US07257699B2
公开(公告)日：2007-08-14
申请号：US11058522
申请日：2005-02-14
CPC分类号： G06F9/3836 , G06F9/30181 , G06F9/30189 , G06F9/3838 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. During normal-execution mode, the processor issues instructions for execution in program order. When the processor encounters a long-latency operation, such as a load miss, the processor records the long-latency operation in a long-latency scoreboard, wherein each entry in the long-latency scoreboard includes a deferred buffer start index. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order. Upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the processor updates a deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction. When a long-latency operation returns, the processor executes instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.
摘要翻译： 本发明的一个实施例提供一种在支持推测执行的处理器中返回长延迟操作之后选择性地执行延迟指令的系统。 在正常执行模式下，处理器以程序顺序发出执行指令。 当处理器遇到诸如加载未命中的长延迟操作时，处理器将长延迟操作记录在长延迟记分板中，其中长延迟记分板中的每个条目包括延迟缓冲器开始索引。 在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟到延迟缓冲器中，并且其中 其他非延迟指令按程序顺序执行。 在遇到取决于长延迟记分板中的长时间延迟操作的延迟指令时，处理器更新与长延迟操作相关联的延迟缓冲器开始索引以指向由延迟指令占用的延迟缓冲器中的位置。 当长延迟操作返回时，处理器执行延迟缓冲区中的指令，从延迟缓冲区起始索引开始，用于返回长延迟操作。
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公开(公告)号：US20070136562A1
公开(公告)日：2007-06-14
申请号：US11364479
申请日：2006-02-27
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： One embodiment of the present invention provides a system which decouples register bypassing from pipeline depth. The system starts by storing an intermediate result generated by an originating instruction to an allocated location in an architectural-commit first-in-first-out (ACFIFO) structure and to an allocated location in a working register file (WRF). The system then bypasses the intermediate result from the WRF to subsequent dependent instructions until the originating instruction retires from the instruction execution pipeline. Next, the system stores the intermediate result from the ACFIFO structure to a location in an ARF when the originating instruction retires from the instruction execution pipeline. The system then removes the intermediate result from the WRF and the ACFIFO structure when the intermediate result has been stored in the ARF.
摘要翻译： 本发明的一个实施例提供了一种使注册器旁路与流水线深度分离的系统。 系统通过将始发指令生成的中间结果存储在架构提交先进先出（ACFIFO）结构中的分配位置和工作寄存器文件（WRF）中的分配位置来开始。 然后，系统将中间结果从WRF旁路到后续的相关指令，直到起始指令从指令执行流水线退出。 接下来，当起始指令从指令执行管线退出时，系统将ACFIFO结构的中间结果存储到ARF中的位置。 当中间结果存储在ARF中时，系统将从WRF和ACFIFO结构中删除中间结果。
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55.发明申请Selectively performing fetches for store operations during speculative execution 有权在投机执行期间选择性地执行存储操作的提取公开(公告)号：US20060020757A1
公开(公告)日：2006-01-26
申请号：US11083264
申请日：2005-03-16
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F12/0862
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
摘要翻译： 本发明的一个实施例提供一种处理器，其在推测执行期间选择性地取出用于存储指令的高速缓存行。 在正常执行期间，处理器以程序顺序发出执行指令。 当遇到产生发射条件的指令时，处理器执行检查点并以推测执行模式开始执行指令。 在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以获得匹配的高速缓存线，并将商店的存储缓冲区检查到匹配的高速缓存行。 如果在L1数据高速缓存中已经存在匹配的高速缓存行，或者如果存储到存储缓冲器中的存储到匹配的高速缓存行，则处理器抑制对高速缓存行的提取的生成。 否则，处理器生成缓存行的提取。
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56.发明授权公开(公告)号：US09256438B2
公开(公告)日：2016-02-09
申请号：US12354206
申请日：2009-01-15
CPC分类号： G06F9/3857 , G06F9/30123 , G06F9/384 , G06F9/3842 , G06F9/3867
摘要： A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.
摘要翻译： 计算机处理器管道具有架构寄存器文件和工作寄存器文件。 在工作寄存器文件中的位置被分配给指令之后，在工作寄存器文件中的条目的寿命由通过流水线中的指定级的预定数量的指令确定。 基于性能特征选择工作寄存器文件的大小。 工作寄存器文件债权人指示器耦合到前端管道部分和后端管道部分。 监视工作寄存器文件信用指示符，以防止工作寄存器文件溢出。 当架构寄存器文件中的一个位置被提前读取时，监视该位置以确定在发出与早期读取相关联的指令之前是否写入位置。
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57.发明申请公开(公告)号：US20100180103A1
公开(公告)日：2010-07-15
申请号：US12354206
申请日：2009-01-15
CPC分类号： G06F9/3857 , G06F9/30123 , G06F9/384 , G06F9/3842 , G06F9/3867
摘要： A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.
摘要翻译： 计算机处理器管道具有架构寄存器文件和工作寄存器文件。 在工作寄存器文件中的位置被分配给指令之后，在工作寄存器文件中的条目的寿命由通过流水线中的指定级的预定数量的指令确定。 基于性能特征选择工作寄存器文件的大小。 工作寄存器文件债权人指示器耦合到前端管道部分和后端管道部分。 监视工作寄存器文件信用指示符，以防止工作寄存器文件溢出。 当架构寄存器文件中的一个位置被提前读取时，监视该位置以确定在发出与早期读取相关联的指令之前是否写入位置。
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58.发明授权Method and apparatus for supporting different modes of multi-threaded speculative execution 有权支持不同模式的多线程推测执行的方法和装置公开(公告)号：US07584346B1
公开(公告)日：2009-09-01
申请号：US11698479
申请日：2007-01-25
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/383 , G06F9/3842 , G06F12/0862
摘要： One embodiment of the present invention provides a system that supports different modes of multi-threaded speculative execution on a processor. The system starts with two or more threads executing in a first multi-threaded speculative-execution mode. The system then switches to a second multi-threaded speculative-execution mode by configuring circuits in the processor to enable a second multi-threaded speculative-execution mode. After configuring the circuits, the system next switches the threads from executing in the first multi-threaded speculative-execution mode to executing in the second multi-threaded speculative-execution mode.
摘要翻译： 本发明的一个实施例提供一种在处理器上支持不同模式的多线程推测性执行的系统。 系统以在第一个多线程推测执行模式下执行的两个或多个线程开始。 然后，系统通过配置处理器中的电路来启用第二多线程推测执行模式，然后切换到第二多线程推测执行模式。 在配置电路之后，系统接下来将线程从第一多线程推测执行模式执行到第二多线程推测执行模式。
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59.发明授权Selectively performing fetches for store operations during speculative execution 有权在投机执行期间选择性地执行存储操作的提取公开(公告)号：US07277989B2
公开(公告)日：2007-10-02
申请号：US11083264
申请日：2005-03-16
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3834 , G06F12/0862
摘要： One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.
摘要翻译： 本发明的一个实施例提供一种处理器，其在推测执行期间选择性地取出用于存储指令的高速缓存行。 在正常执行期间，处理器以程序顺序发出执行指令。 当遇到产生发射条件的指令时，处理器执行检查点并以推测执行模式开始执行指令。 在推测执行模式期间遇到存储指令时，处理器检查L1数据高速缓存以获得匹配的高速缓存线，并将商店的存储缓冲区检查到匹配的高速缓存行。 如果在L1数据高速缓存中已经存在匹配的高速缓存行，或者如果存储到存储缓冲器中的存储到匹配的高速缓存行，则处理器抑制对高速缓存行的提取的生成。 否则，处理器生成缓存行的提取。
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60.发明授权Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor 有权用于在执行前处理器中避免读取后读数危险的方法和装置公开(公告)号：US07216219B2
公开(公告)日：2007-05-08
申请号：US10923218
申请日：2004-08-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3863 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： One embodiment of the present invention provides a system that avoids write-after-read (WAR) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint, defers the instruction, and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and wherein other non-deferred instructions are executed in program order. While deferring the instruction, the system stores the instruction along with any resolved source operands for the instruction into a deferred buffer.
摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免读后读取（WAR）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生检查点，延迟指令并执行执行模式中的后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他 非递延指令按程序顺序执行。 在延迟指令的同时，系统将指令与指令的任何解析的源操作数一起存储到延迟缓冲区中。
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