Rotatable orientation independent gravity sensor and methods for correcting systematic errors
    51.
    发明授权
    Rotatable orientation independent gravity sensor and methods for correcting systematic errors 失效
    可旋转取向独立重力传感器和校正系统误差的方法

    公开(公告)号:US08131494B2

    公开(公告)日:2012-03-06

    申请号:US12328181

    申请日:2008-12-04

    IPC分类号: G01R35/00

    摘要: A method to correct for a systematic error of a sensor having a plurality of accelerometers configured to measure gravitational acceleration, the method including: rotating the plurality of accelerometers about a first axis; obtaining a first set of calibration measurements from the plurality of accelerometers from the rotation about the first axis; determining a first systematic error for each accelerometer in the plurality using the first set of calibration measurements; and removing the first systematic error from sensor measurements to correct for the systematic error.

    摘要翻译: 一种用于校正具有被配置为测量重力加速度的多个加速度计的传感器的系统误差的方法,所述方法包括:围绕第一轴旋转所述多个加速度计; 从围绕第一轴的旋转获得来自多个加速度计的第一组校准测量; 使用所述第一组校准测量来确定所述多个中的每个加速度计的第一系统误差; 并从传感器测量中去除第一个系统误差,以纠正系统误差。

    Method, System and Terminal for Accessing Packet Data Serving Node
    52.
    发明申请
    Method, System and Terminal for Accessing Packet Data Serving Node 有权
    用于访问分组数据服务节点的方法,系统和终端

    公开(公告)号:US20120044920A1

    公开(公告)日:2012-02-23

    申请号:US13258005

    申请日:2009-12-04

    IPC分类号: H04W40/00

    摘要: The present invention discloses a method, system and terminal for accessing a Packet Data Serving Node. Said method comprises: directly accessing a service server to register through a WIFI module; receiving returned parameter information; carrying out PPP encapsulation for request information for establishing the PPP link to generate a first data packet; encapsulating said first data packet with one layer of TUNNEL header to generate a second data packet; encapsulating said second data packet with one layer of IP header based on a WIFI link to generate a third data packet and sending said third data packet to a WAG through a WIFI link; said third data packet being used for analyzing and dropping the IP header and TUNNEL header of said third data packet to recover the first data packet after being received by WAG, and recovered first data packet is analyzed by PDSN to establish a link connection.

    摘要翻译: 本发明公开了一种用于访问分组数据服务节点的方法,系统和终端。 所述方法包括:通过WIFI模块直接访问业务服务器进行注册; 接收返回的参数信息; 对建立PPP链路的请求信息进行PPP封装,生成第一数据包; 用一层TUNNEL头封装所述第一数据分组以产生第二数据分组; 基于WIFI链路封装具有一层IP报头的所述第二数据分组,以生成第三数据分组,并通过WIFI链路将所述第三数据分组发送到WAG; 所述第三数据分组用于分析和删除所述第三数据分组的IP报头和TUNNEL报头,以在由WAG接收之后恢复第一数据分组,并且由PDSN分析恢复的第一数据分组以建立链路连接。

    Apparatus and Method for Reducing Effects of Eccentricity in Induction Tools
    53.
    发明申请
    Apparatus and Method for Reducing Effects of Eccentricity in Induction Tools 有权
    降低感应工具偏心效应的装置和方法

    公开(公告)号:US20110006775A1

    公开(公告)日:2011-01-13

    申请号:US12832678

    申请日:2010-07-08

    IPC分类号: G01V3/18

    CPC分类号: G01V3/28

    摘要: In aspects, an apparatus for use in a wellbore for determining a property of an earth formation is provided. The apparatus, in one embodiment, may include a tool body including a transmitter configured to induce electromagnetic waves in an earth formation, a receiver configured to provide signals responsive to the induced electromagnetic waves, a conductive member between the transmitter and the receiver extending radially from the tool body and configured to reduce propagation of eddy currents between the transmitter and the receiver when the tool body is in a wellbore and a processor configured to process the signals provided by the receiver to determine the property of the earth formation.

    摘要翻译: 在方面中,提供了一种用于确定地层的性质的井眼中的装置。 在一个实施例中,该装置可以包括工具主体,其包括被配置为在地层中诱发电磁波的发射器,被配置为提供响应于感应的电磁波的信号的接收器,发射器和接收器之间的导电部件从 所述工具主体并且被配置为当所述工具主体处于井筒中时,减少所述发射器和所述接收器之间的涡流的传播,并且所述处理器被配置为处理由所述接收器提供的信号以确定所述地层的性质。

    DETERMINATION OF GAS SATURATION RADIAL PROFILE FROM MULTI-FREQUENCY NMR DATA
    54.
    发明申请
    DETERMINATION OF GAS SATURATION RADIAL PROFILE FROM MULTI-FREQUENCY NMR DATA 有权
    从多频谱数据中确定气体饱和辐射剖面

    公开(公告)号:US20080234937A1

    公开(公告)日:2008-09-25

    申请号:US11689887

    申请日:2007-03-22

    IPC分类号: G01V3/38 G01V3/14

    摘要: A method for determining fluid saturation in a formation at a plurality of radial depths near a wellbore, the method including: obtaining multi-frequency nuclear magnetic resonance (NMR) response data for the formation; and processing the data to determine simultaneously the fluid saturation at each radial depth. A computer program product is provided.

    摘要翻译: 一种用于确定井眼附近的多个径向深度处的地层中的流体饱和度的方法,所述方法包括:获得用于地层的多频核磁共振(NMR)响应数据; 并处理数据以同时确定每个径向深度处的流体饱和度。 提供计算机程序产品。

    Selectable multi-input CMOS data register
    55.
    发明授权
    Selectable multi-input CMOS data register 失效
    可选择多输入CMOS数据寄存器

    公开(公告)号:US4692634A

    公开(公告)日:1987-09-08

    申请号:US856920

    申请日:1986-04-28

    申请人: Sheng Fang Sam H. Lee

    发明人: Sheng Fang Sam H. Lee

    CPC分类号: H03K3/35625 G11C19/28

    摘要: A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals.

    摘要翻译: CMOS数据寄存器包括主级和从级。 主级由第一传输门和第一存储设备组成。 从站由第二传输门,第二存储设备和第三传输门形成。 传输门和存储设备由一种导电性的MOS晶体管形成,这降低了布局的复杂性并减少了所需的芯片面积。 数据寄存器由较少数量的晶体管元件组成,从而减少时钟信号的负载。

    Balanced CMOS logic circuits
    56.
    发明授权
    Balanced CMOS logic circuits 失效
    平衡CMOS逻辑电路

    公开(公告)号:US4620117A

    公开(公告)日:1986-10-28

    申请号:US688781

    申请日:1985-01-04

    申请人: Sheng Fang

    发明人: Sheng Fang

    摘要: A logic gate circuit composed of CMOS transistors includes at least a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes. The logic gate circuit further includes at least a second pair of transistors formed of third and fourth transistors of the same conductivity as the first pair and having gate, source and drain electrodes. The source and drain electrodes of the first and second pairs are adapted to receive input signals. A pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary electrodes are provided. The gate of the fifth transistor is connected to the drain of the sixth transistor, and the gate of the sixth transistor is connected to the drain of the fifth transistor. The drain of the fifth transistor is further connected to the drains of the first and second transistors and to a true output terminal. The drain of the sixth transistor is further connected to the drains of the third and fourth transistors and to a complement output terminal. All of the first through sixth transistors are arranged on an integrated circuit substrate with topological regularity.

    摘要翻译: 由CMOS晶体管构成的逻辑门电路至少包括由具有栅极,源极和漏极的一种导电类型的第一和第二晶体管形成的第一对晶体管。 逻辑门电路还包括至少第二对晶体管,其由与第一对导电性相同的第三和第四晶体管形成,并具有栅极,源极和漏极。 第一和第二对的源极和漏极适于接收输入信号。 提供由互补电极的第五和第六晶体管形成的一对交叉耦合晶体管。 第五晶体管的栅极连接到第六晶体管的漏极,第六晶体管的栅极连接到第五晶体管的漏极。 第五晶体管的漏极还连接到第一和第二晶体管的漏极,并连接到真实的输出端子。 第六晶体管的漏极还连接到第三和第四晶体管的漏极以及补码输出端。 所有第一至第六晶体管都布置在具有拓扑规律性的集成电路基板上。

    Byte wide EEPROM with individual write circuits and write prevention
means
    57.
    发明授权
    Byte wide EEPROM with individual write circuits and write prevention means 失效
    具有单独写入电路和写保护装置的字节宽EEPROM

    公开(公告)号:US4599707A

    公开(公告)日:1986-07-08

    申请号:US585319

    申请日:1984-03-01

    申请人: Sheng Fang

    发明人: Sheng Fang

    CPC分类号: G11C16/28 G11C16/10

    摘要: An array arrangement for EEPROMS in which each memory cell has two transistors. Selection is simplified whereby in selecting a cell all of the cells in the selected row are connected to one terminal of the writing circuit and all the cells in the selected column are connected to the other terminal. This selection process prevents any cell from being written into except the cell at the intersection of the selected row and the selected column.

    摘要翻译: 用于EEPROMS的阵列布置,其中每个存储单元具有两个晶体管。 简化了选择,在选择单元格时,所选行中的所有单元都连接到写入电路的一个端子,并且所选列中的所有单元都连接到另一个端子。 该选择过程可以防止任何单元格被写入除了所选行和所选列的交点之外的单元格。