公开(公告)号：US06838903B1

公开(公告)日：2005-01-04

申请号：US10608454

申请日：2003-06-26

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A logic block in a field programmable gate array comprises a plurality of clusters of logic devices. At least one of the logic devices in each of the clusters has an input or an output. A first set of interconnect conductors enters the logic block from a first side and forming a programmable intersection with the input or the output of at least one of the logic devices in each of the clusters. A second set of interconnect conductors enters the logic block from a second side and forming a programmable intersection with the input or output of one of the logic devices in each cluster, the first set of interconnect conductors forming a pairwise hardwired connection with the second set of interconnect conductors. An interconnect conductor splitting extension is disposed between the first set of interconnect conductors and the second set of interconnect conductors.

Abstract translation: 现场可编程门阵列中的逻辑块包括多个逻辑器件群集。 每个集群中的至少一个逻辑设备具有输入或输出。 第一组互连导体从第一侧进入逻辑块，并且形成与每个簇中的至少一个逻辑器件的输入或输出的可编程交叉。 第二组互连导体从第二侧进入逻辑块并且与每个簇中的逻辑器件中的一个的输入或输出形成可编程交叉，第一组互连导体与第二组互连导体形成成对的硬连线连接 互连导体。 互连导体分裂延伸部设置在第一组互连导体和第二组互连导体之间。

公开(公告)号：US06624657B2

公开(公告)日：2003-09-23

申请号：US09880679

申请日：2001-06-12

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A logic block in a field programmable gate array comprises a plurality of clusters of logic devices. At least one of the logic devices in each of the clusters has an input or an output. A first set of interconnect conductors enters the logic block from a first side and forming a programmable intersection with the input or the output of at least one of the logic devices in each of the clusters. A second set of interconnect conductors enters the logic block from a second side and forming a programmable intersection with the input or output of one of the logic devices in each cluster, the first set of interconnect conductors forming a pairwise hardwired connection with the second set of interconnect conductors. An interconnect conductor splitting extension is disposed between the first set of interconnect conductors and the second set of interconnect conductors.

公开(公告)号：US06268743B1

公开(公告)日：2001-07-31

申请号：US09518974

申请日：2000-03-06

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19177

CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/17796

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF . Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of DFF, and symmetrized with the output of the DFF to form first and second outputs of each of the clusters.

Abstract translation: FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中间层次的路由资源是包括互连导体组的高速公路路由信道M1，M2和M3。 在半层次FPGA架构的最底层，存在块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导体，以将逻辑元件连接到更多的路由资源。 每个B1块包括四组设备。 四个群集中的每一个包括第一和第二LUT3，LUT2和DFF。 每个LUT3具有第一，第二和第三输入和单个输出。 每个LUT2具有第一和第二输入和单个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT3的输出与DFF的输入混合，并且与DFF的输出对称，以形成每个簇的第一和第二输出。

公开(公告)号：US5477165A

公开(公告)日：1995-12-19

申请号：US332550

申请日：1994-12-28

Applicant: Khaled A. ElAyat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

Inventor： Khaled A. ElAyat ,  Gregory W. Bakker ,  Jung-Cheun Lien ,  William C. Plants ,  Sinan Kaptanoglu ,  Runip Gopisetty ,  King W. Chan ,  Marko Chew

IPC: H03K19/177 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/173

CPC classification number: G01R31/2884 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17728

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Abstract translation: 用户可编程门阵列架构包括可包括一个或多个组合和/或顺序逻辑电路的逻辑功能模块阵列。 包括多个水平和垂直通用互连通道的互连架构，每个通道互连通道包括多个互连导体，其中一些互连导体可能被分段，其被施加在阵列上。 互连导体中的单个导体可通过用户可编程互连元件彼此连接并连接到逻辑功能模块的输入和输出端。 包括本地互连通道的本地互连架构也被施加在阵列上。 每个局部互连通道包括多个局部互连导体并且在相邻的逻辑功能模块对之间运行。

公开(公告)号：US5448185A

公开(公告)日：1995-09-05

申请号：US144452

申请日：1993-10-27

Applicant: Sinan Kaptanoglu

Inventor： Sinan Kaptanoglu

IPC: H03K19/173 ,  G06F7/575 ,  H03K19/177

CPC classification number: G06F7/575 ,  H03K19/17704 ,  H03K19/17744 ,  G06F2207/3896

Abstract: According to the present invention, a plurality of programmable multi-bit output functional block modules, each capable of assuming the functionality of one of the set of adders, subtracters, magnitude comparators, identity comparators, up/down counters, registers, multi-bit ANDs, and similar devices, are placed in predetermined locations of the FPGA chip. The number of functional blocks is much fewer than the number of FPGA modules on the chip. Each of the functional blocks has a plurality of inputs and outputs, each of which is capable of being connected to the neighboring programmable interconnect resources. Communication between and amongst functional blocks is carried out with the standard programmable resources available on board the FPGA chip.

Abstract translation: 根据本发明，多个可编程多位输出功能块模块，每个能够假设加法器，减法器，幅度比较器，同步比较器，上/下计数器，寄存器，多位 AND和类似设备放置在FPGA芯片的预定位置。 功能块的数量远低于芯片上FPGA模块的数量。 每个功能块具有多个输入和输出，每个输入和输出能够连接到相邻的可编程互连资源。 功能块之间和之间的通信使用FPGA芯片上可用的标准可编程资源进行。

公开(公告)号：US5073729A

公开(公告)日：1991-12-17

申请号：US542722

申请日：1990-06-22

Applicant: Johathan W. Greene ,  Abbas A. El Gamal ,  Sinan Kaptanoglu

Inventor： Johathan W. Greene ,  Abbas A. El Gamal ,  Sinan Kaptanoglu

IPC: H01L21/82 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  G06F17/5077 ,  H03K19/17704

Abstract: A segmented routing architecture includes three or more different interior segment lengths within all of the segmented tracks in a channel. Four or more different segment lengths of interior segments are present in a channel if the sole segment in each unsegmented track is considered, too. Two or more different segment lengths of interior segments exist within a single wiring track. Lengths of adjacent segments within a track are balanced with a ratio not exceeding about two. In any given channel, the average length of all the segments in each column is relatively low in the interior and increases substantially monotonically towards the ends of the channel.

公开(公告)号：US08593174B1

公开(公告)日：2013-11-26

申请号：US13539007

申请日：2012-06-29

Applicant: James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

Inventor： James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  G06F7/50 ,  H03K19/017581

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract translation: 公开了可以提供多个有利特征的逻辑元件（LE）。 例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

公开(公告)号：US08237465B1

公开(公告)日：2012-08-07

申请号：US13050732

申请日：2011-03-17

Applicant: James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

Inventor： James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  G06F7/50 ,  H03K19/017581

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract translation: 公开了可以提供多个有利特征的逻辑元件（LE）。 例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

公开(公告)号：US07924053B1

公开(公告)日：2011-04-12

申请号：US12362844

申请日：2009-01-30

Applicant: Sinan Kaptanoglu ,  Wenyi Feng

Inventor： Sinan Kaptanoglu ,  Wenyi Feng

IPC: H01L25/00

CPC classification number: H03K19/177

Abstract: A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group. Groups are pitch matched to logic function generators to optimize and modularize area. Provision is made for global and local control of the sequential elements.

Abstract translation: 公开了一种用于现场可编程门阵列集成电路器件的逻辑集群。 集群包括多个功能块和三个级别的路由多路复用器。 外部信号主要进入第三级多路复用器的逻辑集群，其中几个信号进入第二级。 组合输出反馈到第一和第二电平复用器，而顺序输出反馈到第三级多路复用器。 逻辑函数发生器具有可变输入，具有不同的传播延迟。 第一和第二级多路复用器之间的路由信号被分组成速度等级并且根据其速度等级耦合到与不同逻辑函数发生器相关联的第一级复用器。 第二和第三级复用器被组织成组，使得第二和第三级多路复用器之间的路由信号可以被定位在该组占用的区域内。 组与逻辑功能发生器匹配，优化和模块化区域。 规定了全局和本地对顺序元素的控制。

公开(公告)号：US07800401B1

公开(公告)日：2010-09-21

申请号：US11841727

申请日：2007-08-20

Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

IPC: H03K19/177

CPC classification number: H03K19/177

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。