公开(公告)号：US10460821B2

公开(公告)日：2019-10-29

申请号：US15896817

申请日：2018-02-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

IPC: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C29/04 ,  G11C29/26

Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

公开(公告)号：US10331826B2

公开(公告)日：2019-06-25

申请号：US15630394

申请日：2017-06-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F17/50 ,  G06G7/62 ,  H03K19/00 ,  H01L23/58 ,  G01R31/28 ,  H01L29/10 ,  H01L25/00 ,  G01R27/28 ,  G01R31/36

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

公开(公告)号：US20160003900A1

公开(公告)日：2016-01-07

申请号：US14637543

申请日：2015-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin Ajit Parekhji

IPC: G01R31/3177

CPC classification number: G01R31/318555 ,  G01R31/31724 ,  G01R31/318566 ,  G01R31/3187

Abstract: Circuits and methods for performing self-test of digital circuits are disclosed. In an embodiment, a method includes applying a set of test patterns for performing scan testing of a digital circuit to generate scan outputs from the digital circuit. The set of test patterns includes one or more sets of base test patterns already stored in a memory and one or more sets of derived test patterns temporarily generated from the one or more sets of base test patterns. The method further includes comparing the scan outputs received from the digital circuit with reference scan outputs corresponding to the digital circuit for fault detection in the digital circuit to thereby achieve a target fault coverage of the scan testing of the digital circuit. The reference scan outputs corresponding to the digital circuit are stored in the memory.

Abstract translation: 公开了用于执行数字电路自检的电路和方法。 在一个实施例中，一种方法包括应用一组用于执行数字电路的扫描测试以产生数字电路的扫描输出的测试图案。 该组测试模式包括已经存储在存储器中的一组或多组基本测试模式以及从一个或多个基本测试模式组临时生成的一组或多组派生测试模式。 该方法还包括将从数字电路接收的扫描输出与数字电路中用于故障检测的数字电路相对应的参考扫描输出进行比较，从而实现数字电路的扫描测试的目标故障覆盖。 对应于数字电路的参考扫描输出存储在存储器中。

公开(公告)号：US09229055B2

公开(公告)日：2016-01-05

申请号：US14743720

申请日：2015-06-18

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。

公开(公告)号：US08839063B2

公开(公告)日：2014-09-16

申请号：US13749623

申请日：2013-01-24

Applicant: Texas Instruments Incorporated

Inventor： Rubin Ajit Parekhji ,  Srivaths Ravi ,  Prakash Narayanan ,  Milan Shetty

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318544 ,  G01R31/318572

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract translation: 公开了一种测试被测设备（DUT）和测试系统的方法。 该方法包括生成与从测试系统接收的测试图案结构相关联的至少一个控制信号。 该方法进一步包括从DUT中的M个I / O端口中选择M1个端口，以基于控制信号接收与测试模式结构相对应的扫描输入，从M个I / O端口中选择M2个端口 以提供基于控制信号的扫描输出，其中M1和M2中的每一个是从0到M中选择的数字，并且其中M1和M2的和小于或等于M.此后，该方法包括执行扫描测试 基于提供给M1端口的扫描输入并从M2端口接收扫描输出的DUT的DUT。