公开(公告)号：US11070197B1

公开(公告)日：2021-07-20

申请号：US16731474

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Gangyao Wang ,  Rajarshi Mukhopadhyay ,  Miguel Aguirre

IPC: H03K3/011 ,  H03K17/687 ,  H03M1/12

Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.

公开(公告)号：US20210203309A1

公开(公告)日：2021-07-01

申请号：US16731474

申请日：2019-12-31

Applicant: Texas Instruments Incorporated

Inventor： Gangyao Wang ,  Rajarshi Mukhopadhyay ,  Miguel Aguirre

IPC: H03K3/011 ,  H03M1/12 ,  H03K17/687

Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.

公开(公告)号：US10651841B2

公开(公告)日：2020-05-12

申请号：US16247146

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Bondade ,  Nathan Schemm ,  Rajarshi Mukhopadhyay

IPC: H03K3/00 ,  H03K17/687 ,  H03K5/1532 ,  H03K5/08 ,  H03K3/0233 ,  H03K5/24 ,  H02M1/08 ,  H03K17/082 ,  H03K17/16

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

公开(公告)号：US10382032B2

公开(公告)日：2019-08-13

申请号：US15714643

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajarshi Mukhopadhyay ,  Sooping Saw ,  Anuj Jain

IPC: H02P6/14 ,  H03K17/16 ,  H02M1/08 ,  H02M1/44 ,  H02P6/08 ,  H02M7/5387 ,  H02M1/00

Abstract: Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

公开(公告)号：US20190172907A1

公开(公告)日：2019-06-06

申请号：US16266677

申请日：2019-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Carothers ,  Ricky Jackson ,  Rajarshi Mukhopadhyay ,  Ben Cook

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/522 ,  H01L49/02

Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

公开(公告)号：US20190149150A1

公开(公告)日：2019-05-16

申请号：US16247146

申请日：2019-01-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajdeep Bondade ,  Nathan Schemm ,  Rajarshi Mukhopadhyay

IPC: H03K17/687 ,  H02M1/08 ,  H03K5/24 ,  H03K5/08 ,  H03K17/082 ,  H03K3/0233 ,  H03K17/16 ,  H03K5/1532

Abstract: An apparatus includes a voltage divider circuit including a plurality of series-connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

公开(公告)号：US20180372508A1

公开(公告)日：2018-12-27

申请号：US16056275

申请日：2018-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arup Polley ,  Srinath Ramaswamy ,  Baher S. Haroun ,  Rajarshi Mukhopadhyay

IPC: G01D5/14 ,  G01D3/036

Abstract: A first amplifier has an input to receive a Hall-signal output current from a first Hall element and has an output to output feedback current in response to the received Hall-signal output current. The Hall-signal output current is impeded by an impedance of the first Hall element. The feedback current is coupled to counterpoise the Hall-signal output current at the input, and a voltage at the output is an amplified Hall output signal. A second amplifier generates a high-frequency portion output signal in response to a difference between the amplified Hall output signal and a Hall-signal output signal from a second Hall element. A filter reduces high-frequency content of the high-frequency portion output signal and generates an offset correction signal. A third amplifier generates a corrected Hall signal in response to a difference between the amplified Hall output signal and the offset correction signal.

公开(公告)号：US10024887B2

公开(公告)日：2018-07-17

申请号：US15245882

申请日：2016-08-24

Applicant: Texas Instruments Incorporated

Inventor： Olivier Trescases ,  Johan Tjeerd Strydom ,  Rajarshi Mukhopadhyay

IPC: H03K17/60 ,  G01R19/00 ,  G01R15/06 ,  H03K17/687 ,  G05F1/571

Abstract: Circuitry and methods for measuring the voltage at a node are disclosed. A capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

公开(公告)号：US20180062510A1

公开(公告)日：2018-03-01

申请号：US15659062

申请日：2017-07-25

Applicant: Texas Instruments Incorporated

Inventor： Olivier Trescases ,  Johan Tjeerd Strydom ,  Rajarshi Mukhopadhyay

IPC: H02M3/156 ,  H03K17/284 ,  H03K17/687

CPC classification number: H02M3/156 ,  G01R19/2509 ,  H03K17/284 ,  H03K17/687

Abstract: Circuitry and methods for sampling a signal are disclosed. An example of the circuitry includes a node for coupling the circuitry to the signal being sampled and a plurality of capacitors, wherein each capacitor is selectively coupled to the node by a switch. An analog-to-digital converter is coupled to the node and is for measuring the voltages of individual ones of the plurality of capacitors and converting the voltages to digital signals. Delay circuitry is coupled to each of the switches, the delay circuitry is for closing one switch at a time for a predetermined period.

公开(公告)号：US20170363693A1

公开(公告)日：2017-12-21

申请号：US15186383

申请日：2016-06-17

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Srinath Ramaswamy ,  Baher S. Haroun ,  Rajarshi Mukhopadhyay

IPC: G01R33/00 ,  G01R33/07

CPC classification number: G01R33/0029 ,  G01R33/075 ,  H03F3/38 ,  H03F3/45995

Abstract: A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.