公开(公告)号：US09432044B1

公开(公告)日：2016-08-30

申请号：US14973902

申请日：2015-12-18

Applicant: Texas Instruments Incorporated

Inventor： Seung Bae Lee ,  Ajit Sharma ,  Srinath Ramaswamy

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/06

CPC classification number: H03M1/1061 ,  H03M1/468 ,  H03M1/687

Abstract: A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.

Abstract translation: 通过使用校准DAC确定第一段中的多个最高有效位（MSB）电容器中的每一个的误差电压来校准多段电容逐次逼近模数转换器（SAR ADC）。 第一段通过衰减电容器连接到第二段。 对应于MSB电容器的每个误差电压被数字化以形成一组数字化的误差电压。 至少第二段中的多个较低有效位（LSB）电容器中的每一个的误差电压通过将数字化误差电压的集合相加以形成误差电压（sum（e））的和并且分配 总和（e）作为每个LSB电容器的误差电压，使得减小衰减电容器的失配。

公开(公告)号：US09401196B1

公开(公告)日：2016-07-26

申请号：US14737247

申请日：2015-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chiraag Juvekar ,  Joyce Kwong ,  Clive Bittlestone ,  Srinath Ramaswamy ,  Stephen K. Heinrich-Barna

IPC: G11C11/22

CPC classification number: H01L43/12 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2211/4013 ,  H01L22/14 ,  H01L27/115

Abstract: Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

Abstract translation: 要永久打印在存储器阵列的存储单元中的只读（“RO”）数据被写入存储器阵列。 然后将一个或多个过应力条件（例如热，过电压，过电流和/或机械应力）施加到存储器阵列或存储器阵列内的各个存储单元。 过应力条件作用于存储单元的一个或多个状态确定元件以压印RO数据。 过应力条件永久地改变状态确定元件的状态确定属性的值，而不会使存储单元的正常操作失效。 状态确定属性的改变值根据RO数据位的状态来偏移单元。 该偏置在细胞读出信号中是可检测的。 预制的铁电随机存取存储器（“FRAM”）阵列被烘烤。 烘焙陷阱电偶极子在与预写数据的状态相对应的方向上取向，并形成了RO数据压印。