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    Barrier layer for FinFET channels
    51.
    发明授权
    Barrier layer for FinFET channels 有权
    FinFET通道的阻挡层

    公开(公告)号：US09214555B2

    公开(公告)日：2015-12-15

    申请号：US13795786

    申请日：2013-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Richard Kenneth Oxland ,  Mark van Dal ,  Martin Christopher Holland ,  Georgios Vellianitis ,  Matthias Passlack

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

    Abstract translation: 具有FinFET的集成电路器件，其通道区域具有低通道的晶体缺陷和电流阻挡层，以改善静电控制。 可选地，在电流阻挡层和通道之间设置由高带隙半导体形成的界面控制层。 本公开还提供了形成具有这些结构的集成电路器件的方法。 所述方法包括通过外延生长形成包括沟道的FinFET鳍，然后氧化鳍的一部分以形成电流阻挡层。

    Barrier Layer for FinFET Channels
    52.
    发明申请
    Barrier Layer for FinFET Channels 有权
    FinFET通道的阻挡层

    公开(公告)号：US20140264592A1

    公开(公告)日：2014-09-18

    申请号：US13795786

    申请日：2013-03-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Richard Kenneth Oxland ,  Mark van Dal ,  Martin Christopher Holland ,  Georgios Vellianitis

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

    Abstract translation: 具有FinFET的集成电路器件，其通道区域具有低通道的晶体缺陷和电流阻挡层，以改善静电控制。 可选地，在电流阻挡层和通道之间设置由高带隙半导体形成的界面控制层。 本公开还提供了形成具有这些结构的集成电路器件的方法。 所述方法包括通过外延生长形成包括沟道的FinFET鳍，然后氧化鳍的一部分以形成电流阻挡层。

    Multigate Device Having Reduced Contact Resistivity
    53.
    发明申请
    Multigate Device Having Reduced Contact Resistivity 有权

    公开(公告)号：US20250015154A1

    公开(公告)日：2025-01-09

    申请号：US18769940

    申请日：2024-07-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Georgios Vellianitis ,  Blandine Duriez

    IPC: H01L29/417 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: An exemplary method includes forming an opening in an interlevel dielectric (ILD) layer. The opening in the ILD layer exposes a doped epitaxial layer. The method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. The doped semiconductor layer partially fills the opening. The method further includes forming a metal-comprising structure that fills a remainder of the opening. The metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. The doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. The in-situ deposition process may implement a temperature less than about 350° C. The doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.

    Semiconductor device
    55.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12148814B2

    公开(公告)日：2024-11-19

    申请号：US18358691

    申请日：2023-07-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Georgios Vellianitis

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092

    Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a crystallographic direction.

    Multigate Device Having Reduced Contact Resistivity
    59.
    发明公开
    Multigate Device Having Reduced Contact Resistivity 审中-公开

    公开(公告)号：US20230215928A1

    公开(公告)日：2023-07-06

    申请号：US18175221

    申请日：2023-02-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Georgios Vellianitis ,  Blandine Duriez

    IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06

    CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823412 ,  H01L29/41733 ,  H01L29/66545 ,  H01L29/78696 ,  H01L29/0673

    Abstract: An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10−9 Ω-cm2.

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