公开(公告)号：US20250151370A1

公开(公告)日：2025-05-08

申请号：US19011247

申请日：2025-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Georgios Vellianitis

IPC: H10D64/68 ,  H10B51/30 ,  H10D30/01 ,  H10D30/62 ,  H10D30/67 ,  H10D62/40 ,  H10D62/854

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

公开(公告)号：US11967647B2

公开(公告)日：2024-04-23

申请号：US17361141

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L21/268 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/268 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66742 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes forming conductive plugs in the source/drain contact openings. The method further includes depositing a light blocking layer over the conductive plugs and the at least one dielectric layer. The method further includes etching the light blocking layer to expose the conductive plugs. The method further includes directing a laser irradiation to the conductive plugs and the light blocking layer. The laser irradiation is configured to activate dopants in the source/drain contact regions.

公开(公告)号：US11764290B2

公开(公告)日：2023-09-19

申请号：US17716425

申请日：2022-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3083 ,  H01L21/76224 ,  H01L21/8258 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a crystallographic direction.

公开(公告)号：US11751487B2

公开(公告)日：2023-09-05

申请号：US16933914

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/00

CPC classification number: H10N52/80 ,  H10B61/10 ,  H10N50/85 ,  H10N52/01 ,  H10N52/101

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

公开(公告)号：US11322495B2

公开(公告)日：2022-05-03

申请号：US16801071

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238

Abstract: A complementary metal-oxide-semiconductor device includes a p-type field effect transistor and an n-type filed effect transistor. The p-type filed effect transistor has a first transistor architecture. The n-type field effect transistor is coupled with the p-type field effect transistor and has a second transistor architecture. The second transistor architecture is different from the first transistor architecture. The p-type field effect transistor and the n-type field effect transistor share a same gate structure.

公开(公告)号：US11302820B2

公开(公告)日：2022-04-12

申请号：US16586790

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

公开(公告)号：US11296236B2

公开(公告)日：2022-04-05

申请号：US16184722

申请日：2018-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/324

Abstract: A semiconductor device includes a substrate, a plurality of nanowires, and a gate stack. The nanowires are over the substrate. Each of the nanowires includes a channel region, the channel region having top and bottom surfaces and a first sidewall between the top and bottom surfaces, in which the first sidewall of the channel region has a (111) crystalline orientation. The gate stack is over the channel regions of the nanowires.

公开(公告)号：US11289477B2

公开(公告)日：2022-03-29

申请号：US15720366

申请日：2017-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Georgios Vellianitis

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and an isolation structure formed around the fin structure. The semiconductor structure further includes a nanowire structure formed over the fin structure and a gate structure formed around the nanowire structure. In addition, a bottommost of the nanowire structure is lower than a top surface of the isolation structure.

公开(公告)号：US20210391469A1

公开(公告)日：2021-12-16

申请号：US16901004

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Blandine Duriez ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a first source region, a first drain region, a first gate, a second source region, a second drain region, a second gate, and a first dielectric layer. The first source region and the first drain region are disposed within the semiconductor substrate. The first gate is disposed over the semiconductor substrate in between the first source region and the first drain region. The second source region and the second drain region are disposed within the semiconductor substrate. The second gate is disposed over the semiconductor substrate in between the second source region and the second drain region. The first dielectric layer is located in between the first gate and the semiconductor substrate, and in between the second gate and the semiconductor substrate, wherein the first dielectric layer extends from a position below the first gate to a position below the second gate.

公开(公告)号：US11018243B2

公开(公告)日：2021-05-25

申请号：US15627568

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Martin Christopher Holland ,  Georgios Vellianitis ,  Mark Van Dal

IPC: H01L29/775 ,  H01L29/80 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of nanowires, a sacrificial material, and an epitaxy structure. The gate structure is disposed on and in contact with the substrate. The nanowires extend through the gate structure. The sacrificial material is separated from the gate structure. The epitaxy structure is in contact with the nanowires, is separated from the substrate, and surrounds the sacrificial material.