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公开(公告)号:US11626485B2
公开(公告)日:2023-04-11
申请号:US17070717
申请日:2020-10-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
IPC: H01L29/06 , H01L27/092 , H01L21/8234 , H01L29/78 , H01L29/66
Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
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52.
公开(公告)号:US20220367291A1
公开(公告)日:2022-11-17
申请号:US17815079
申请日:2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chung-Wei Hsu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Hou-Yu Chen , Ching-Wei Tsai , Chih-Hao Wang , Lung-Kun Chu , Mao-Lin Huang , Jia-Ni Yu
IPC: H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/786 , H01L29/78 , H01L21/02 , H01L21/311 , H01L21/28 , H01L29/66 , H01L27/092
Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
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公开(公告)号:US11502168B2
公开(公告)日:2022-11-15
申请号:US16819632
申请日:2020-03-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chung-Wei Hsu , Hou-Yu Chen , Chih-Hao Wang , Ching-Wei Tsai , Kuo-Cheng Chiang , Kuan-Lun Cheng , Mao-Lin Huang , Jia-Ni Yu , Lung-Kun Chu
IPC: H01L29/06 , H01L27/088 , H01L29/10 , H01L29/423 , H01L29/08 , H01L29/49 , H01L21/8234 , H01L21/285 , H01L21/311 , H01L21/28
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material. The first gate electrode structure also includes a passivation layer that completely surrounds the first and second conductive rings, is arranged directly between the first and second nanosheet channel structures, and comprises a second material different than the first material.
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公开(公告)号:US20220328652A1
公开(公告)日:2022-10-13
申请号:US17849952
申请日:2022-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chung-Wei Hsu , Kuo-Cheng Chiang , Lung-Kun Chu , Mao-Lin Huang , Jia-Ni Yu , Chih-Hao Wang
Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.
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公开(公告)号:US20220181218A1
公开(公告)日:2022-06-09
申请号:US17682298
申请日:2022-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung-Kun Chu , Mao-Lin Huang , Wei-Hao Wu , Kuo-Cheng Chiang
IPC: H01L21/8238 , H01L21/3213 , H01L29/423 , H01L27/092 , H01L29/40
Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.
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公开(公告)号:US11257815B2
公开(公告)日:2022-02-22
申请号:US16874907
申请日:2020-05-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Mao-Lin Huang , Chih-Hao Wang , Kuo-Cheng Chiang , Jia-Ni Yu , Lung-Kun Chu , Chung-Wei Hsu
IPC: H01L27/088 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/02 , H01L21/8234 , H01L29/66
Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.
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公开(公告)号:US11244871B2
公开(公告)日:2022-02-08
申请号:US16454598
申请日:2019-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuo-Cheng Chiang , Chung-Wei Hsu , Lung-Kun Chu , Mao-Lin Huang , Jia-Ni Yu , Chih-Hao Wang
IPC: H01L21/8238 , H01L21/02 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78
Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second semiconductor nanosheets in p-type and n-type device regions, respectively. An n-type work function layer is deposited to surround each of the first and second semiconductor nanosheets. A passivation layer is deposited on the n-type work function layer to surround each of the first and second semiconductor nanosheets. A patterned mask is formed on the passivation layer in the n-type device region, and the n-type work function layer and the passivation layer in the p-type device region are removed in an etching process using the patterned mask as an etching mask. Then, the patterned mask is removed, and a p-type work function layer is deposited to surround the first semiconductor nanosheets and to cover the passivation layer.
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公开(公告)号:US20220037499A1
公开(公告)日:2022-02-03
申请号:US17504206
申请日:2021-10-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Chih-Hao Wang
IPC: H01L29/423 , H01L21/28 , H01L21/3205 , H01L21/8234 , H01L27/088 , H01L29/49 , H01L29/66 , H01L29/78
Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.
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公开(公告)号:US20210366783A1
公开(公告)日:2021-11-25
申请号:US16879613
申请日:2020-05-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Chih-Hao Wang
IPC: H01L21/8238 , H01L29/417 , H01L29/66 , H01L29/78 , H01L27/092
Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.
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60.
公开(公告)号:US20210359091A1
公开(公告)日:2021-11-18
申请号:US17218503
申请日:2021-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chung-Wei Hsu , Lung-Kun Chu , Mao-Lin Huang , Jia-Ni Yu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
IPC: H01L29/417 , H01L29/786 , H01L29/423 , H01L21/8234
Abstract: A semiconductor device includes a first interconnect structure; multiple channel layers stacked over the first interconnect structure; a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature between the bottommost one of the channel layers and the first conductive via.
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