公开(公告)号：US20200052084A1

公开(公告)日：2020-02-13

申请号：US16655079

申请日：2019-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20190115438A1

公开(公告)日：2019-04-18

申请号：US16206730

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20190067444A1

公开(公告)日：2019-02-28

申请号：US15691437

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US20180366465A1

公开(公告)日：2018-12-20

申请号：US15996740

申请日：2018-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04 ,  H01L29/78 ,  H01L29/161

Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.

公开(公告)号：US20180350969A1

公开(公告)日：2018-12-06

申请号：US15629885

申请日：2017-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16

Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.

公开(公告)号：US20240145470A1

公开(公告)日：2024-05-02

申请号：US18406025

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0883 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20230335623A1

公开(公告)日：2023-10-19

申请号：US18298073

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L29/6681 ,  H01L27/0924 ,  H01L29/0653 ,  H01L21/823821 ,  H01L21/823878 ,  H10B10/12

Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.

公开(公告)号：US20230117420A1

公开(公告)日：2023-04-20

申请号：US18068203

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US20220336455A1

公开(公告)日：2022-10-20

申请号：US17810341

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung LIN ,  Yi-Hsun CHIU ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Yu-Xuan HUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/76

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

公开(公告)号：US20210336012A1

公开(公告)日：2021-10-28

申请号：US16948712

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.