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公开(公告)号：US5978941A
公开(公告)日：1999-11-02
申请号：US913338
申请日：1997-09-11
CPC分类号： G11C16/3495 , G11C16/14 , G11C16/349 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C29/52 , G11C29/56012 , G11C16/04
摘要： In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction. According to the present invention, the substantial deterioration of each cell can be determined, and such control is possible that more deteriorated memory is used less frequently while less deteriorated memory is used more frequently. As a result, the reliability of the memory is improved, and the memory can have a longer service life.
摘要翻译： PCT No.PCT / JP95 / 00429 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT 1995年3月15日PCT PCT。 出版物WO96 / 28826 日期1996年9月19日在使用电可重写非易失性存储器作为存储介质的存储器件中，为了使存储器均匀地劣化，测量擦除时间和写入时间，存储器中的单元散射的影响 基于所得到的测量值消除，从而以高精度确定了显着的劣化程度，从而实际上获得了高可靠性和高效率的存储器件。 为了重写可重写的非易失性存储器（1），提供了一种用于测量擦除时间和写入时间的装置，用于将擦除时间与存储的基准时间进行比较的装置，用于基于 比较结果，以及根据校正结果确定劣化的方法。 根据本发明，可以确定每个单元的实质性劣化，并且可以更频繁地使用较少劣化的存储器，因此可以更少地使用更恶化的存储器，并且可以进行这种控制。 结果，提高了存储器的可靠性，并且存储器可以具有更长的使用寿命。
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公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译： 一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统， 对连续扇区数据的读命令作出响应。
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公开(公告)号：US06199187B1
公开(公告)日：2001-03-06
申请号：US09544609
申请日：2000-04-06
IPC分类号： H03M1300
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.
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公开(公告)号：US07616485B2
公开(公告)日：2009-11-10
申请号：US11931881
申请日：2007-10-31
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
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公开(公告)号：US06728138B2
公开(公告)日：2004-04-27
申请号：US10373872
申请日：2003-02-27
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。
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公开(公告)号：US6031758A
公开(公告)日：2000-02-29
申请号：US125547
申请日：1998-12-23
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.
摘要翻译： PCT No.PCT / JP96 / 03501 Sec。 371日期1998年12月23日第 102（e）1998年12月23日PCT PCT 1996年11月29日PCT公布。 公开号WO97 / 32253 日期1997年9月4日具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。
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公开(公告)号：US5732208A
公开(公告)日：1998-03-24
申请号：US679960
申请日：1996-07-15
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N-1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N-th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N-1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N-th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N-th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.
摘要翻译： 获得高速存储器访问和使用单个纠错装置的透明错误检测和校正。 主计算机在第一存储器和第二存储器之一（例如，由一个或多个存储器构成）和另一个存储器中的第2N（偶数）扇区数据之一中写入（第2N-1）（奇数）扇区数据 的第一和第二个记忆。 因此，可以将第2N-1扇区数据从第一存储器和第二存储器之一读出到主计算机，并且同时（即，同时），第2N个扇区数据（即，下一个扇区数据 由主计算机读取）能够从第一存储器和第二存储器中的另一个读出，并且可以在纠错装置中执行错误检测和校正。 此外，在下一周期中，从第一存储器和第二存储器之一读出的第2N（偶数）扇区数据可以被输出到主计算机，并且同时（即同时），错误检测 并且可以在错误校正装置中执行从第一计算机和第二计算机之一读出的（2N + 1）扇区数据（由主计算机读取的下一个扇区数据）的纠错。 因此，主计算机总是读取扇区数据，并且同时进行下一个扇区数据的错误检测和纠错，从而显着地减少错误检测和纠错所需的时间（即，使 主计算机2）和存储器访问。
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公开(公告)号：US08503235B2
公开(公告)日：2013-08-06
申请号：US13298548
申请日：2011-11-17
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。
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公开(公告)号：US20100177579A1
公开(公告)日：2010-07-15
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C29/04
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译： 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。
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公开(公告)号：US20070168782A1
公开(公告)日：2007-07-19
申请号：US11599388
申请日：2006-11-15
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译： 一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统， 对连续扇区数据的读命令作出响应。
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